ページ1に含まれる内容の要旨
®
CY62146E MoBL
4-Mbit (256K x 16) Static RAM
mode reduces power consumption by more than 99% when
Features
deselected (CE HIGH). The input and output pins (IO through
0
IO ) are placed in a high impedance state when:
■ Very high speed: 45 ns
15
■ Deselected (CE HIGH)
■ Wide voltage range: 4.5V–5.5V
■ Ultra low standby power ■ Outputs are disabled (OE HIGH)
❐ Typical standby current: 1 μA
■ Both Byte High Enable and Byte Low Enable are disabled
❐ Maximum standby current: 7 μA
(BHE, BLE HIGH)
■
ページ2に含まれる内容の要旨
® CY62146E MoBL Pin Configuration [1] Figure 1. 44-Pin TSOP II (Top View) A A 1 44 4 5 A A 2 43 6 3 A A 3 42 7 2 A 4 OE 1 41 A 5 40 BHE 0 6 39 CE BLE IO 7 38 IO 0 15 IO 8 37 IO 1 14 IO 9 36 IO 2 13 IO 10 IO 35 3 12 V 11 34 V CC SS V 12 SS 33 V CC IO 13 32 IO 4 11 IO 14 IO 5 31 10 IO IO 6 15 30 9 IO 16 29 IO 7 8 WE 17 28 NC A 17 18 27 A 8 A 16 19 26 A 9 A 15 A 20 25 10 A 14 A 21 24 11 A 13 22 23 A 12 Product Portfolio Power Dissipation V Range (V) Operating I , (mA) CC CC Speed Standby, I SB
ページ3に含まれる内容の要旨
® CY62146E MoBL [3, 4] DC Input Voltage .......................................–0.5V to 6.0V Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA Exceeding maximum ratings may impair the useful life of the Static Discharge Voltage............................................ >2001V device. These user guidelines are not tested. (MIL-STD-883, Method 3015) Storage Temperature.................................. –65°C to +150°C Latch up Current...........................
ページ4に含まれる内容の要旨
® CY62146E MoBL Figure 2. AC Test Loads and Waveforms R1 ALL INPUT PULSES V V CC CC 90% 90% OUTPUT 10% 10% GND Fall Time = 1 V/ns R2 Rise Time = 1 V/ns 30 pF INCLUDING JIG AND Equivalent to: THÉ VENIN EQUIVALENT SCOPE R TH OUTPUT V TH Parameters 5.0V Unit R1 1800 Ω R2 990 Ω R 639 Ω TH V 1.77 V TH Data Retention Characteristics Over the Operating Range [2] Parameter Description Conditions Min Typ Max Unit V for Data Retention 2 V V DR CC [6] V = 2V, CE > V – 0.2V, 17 μA I Data Retention Curren
ページ5に含まれる内容の要旨
® CY62146E MoBL Switching Characteristics [9, 10] Over the Operating Range 45 ns (Ind’l/Auto-A) Parameter Description Unit Min Max Read Cycle t Read Cycle Time 45 ns RC t Address to Data Valid 45 ns AA t Data Hold from Address Change 10 ns OHA t CE LOW to Data Valid 45 ns ACE t OE LOW to Data Valid 22 ns DOE [11] t OE LOW to LOW-Z 5ns LZOE [11, 12] t OE HIGH to High-Z 18 ns HZOE [11] t CE LOW to Low-Z 10 ns LZCE [11, 12] t CE HIGH to High-Z 18 ns HZCE t CE LOW to Power Up 0 ns PU t CE HIGH to
ページ6に含まれる内容の要旨
® CY62146E MoBL Switching Waveforms [14, 15] Figure 4. Read Cycle No.1: Address Transition Controlled. t RC RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID [15, 16] Figure 5. Read Cycle No. 2: OE Controlled ADDRESS t RC CE t PD t t HZCE ACE OE t HZOE t DOE t LZOE BHE/BLE t HZBE t DBE t LZBE HIGH IMPEDANCE HIGHI MPEDANCE DATA VALID DATA OUT t LZCE t PU I CC V 50% CC 50% I SUPPLY SB CURRENT Notes , CE = V , BHE, BLE, or both = V . 14. The device is continuously selected. OE IL
ページ7に含まれる内容の要旨
® CY62146E MoBL Switching Waveforms (continued) [13, 17, 18] Figure 6. Write Cycle No 1: WE Controlled t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE t BW BHE/BLE OE t HD t SD NOTE 19 DATA IN DATA IO t HZOE [13, 17, 18] Figure 7. Write Cycle 2: CE Controlled t WC ADDRESS t SCE CE t SA t t AW HA t PWE WE t BW BHE/BLE OE t t SD HD DATA DATA IO NOTE 19 IN t HZOE Notes 17. Data IO is high impedance if OE = V . IH 18. If CE goes HIGH simultaneously with WE = V , the output remains in a high impeda
ページ8に含まれる内容の要旨
® CY62146E MoBL Switching Waveforms (continued) [18] Figure 8. Write Cycle 3: WE controlled, OE LOW t WC ADDRESS t SCE CE t BW BHE/BLE t t AW HA t t SA PWE WE t HD t SD DATA IO NOTE 19 DATA IN t LZWE t HZWE [18] Figure 9. Write Cycle 4: BHE/BLE Controlled, OE LOW t WC ADDRESS CE t SCE t t AW HA t BW BHE/BLE t SA t PWE WE t HZWE t HD t SD NOTE 19 DATA DATA IO IN t LZWE Document Number: 001-07970 Rev. *D Page 8 of 11 [+] Feedback [+] Feedback
ページ9に含まれる内容の要旨
® CY62146E MoBL Table 1. Truth Table CE WE OE BHE BLE Inputs/Outputs Mode Power ) H X X X X High-Z Deselect/Power down Standby (I SB ) L X X H H High-Z Output Disabled Active (I CC –IO ) Read Active (I ) L H L L L Data Out (IO 0 15 CC –IO ); ) LH LH L Data Out (IO Read Active (I 0 7 CC IO –IO in High-Z 8 15 L H L L H Data Out (IO –IO ); Read Active (I ) 8 15 CC IO –IO in High-Z 0 7 L H H L L High-Z Output Disabled Active (I ) CC L H H H L High-Z Output Disabled Active (I ) CC L H H L H High-Z
ページ10に含まれる内容の要旨
® CY62146E MoBL Package Diagrams Figure 10. 44-Pin TSOP II, 51-85087 51-85087-*A Document Number: 001-07970 Rev. *D Page 10 of 11 [+] Feedback [+] Feedback
ページ11に含まれる内容の要旨
® CY62146E MoBL Document History Page ® Document Title: CY62146E MoBL 4-Mbit (256K x 16) Static RAM Document Number: 001-07970 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 463213 See ECN NXR New Data Sheet *A 684343 See ECN VKN Added Preliminary Automotive-A Information Updated Ordering Information Table *B 925501 See ECN VKN Added footnote #8 related to I and I SB2 CCDR Added footnote #13 related AC timing parameters *C 1045260 See ECN VKN Converted Automotive-A specs from
