ページ1に含まれる内容の要旨
CY62136EV30
®
MoBL
2-Mbit (128K x 16) Static RAM
[1]
Features Functional Description
• Very high speed: 45 ns The CY62136EV30 is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features
• Wide voltage range: 2.20V–3.60V
advanced circuit design to provide ultra-low active current.
®
• Pin-compatible with CY62136CV30
This is ideal for providing More Battery Life™ (MoBL ) in
portable applications such as cellular telephones. The device
• Ultra low standby power
ページ2に含まれる内容の要旨
CY62136EV30 ® MoBL [2, 3] Pin Configuration VFBGA (Top View) 44 TSOP II (Top View) 1 2 4 5 3 6 1 44 A A 4 5 A A A NC A 43 A BLE OE 2 0 1 2 A 3 6 3 42 A A 2 7 4 41 A OE 1 A A I/O BHE CE I/O B 8 3 4 0 40 5 BHE A 0 39 CE 6 BLE 38 A C I/O 7 I/O I/O I/O A I/O I/O 0 15 10 5 6 1 2 9 37 I/O 8 I/O 1 14 36 I/O 9 2 I/O 13 Vcc A V I/O NC I/O SS D 11 7 3 35 10 I/O I/O 3 12 34 V 11 V SS CC 33 V 12 Vss V NC A SS V I/O E CC CC I/O 12 16 4 I/O 13 32 I/O 4 11 I/O 31 I/O 14 10 5 F I/O I/O A A I/O 30 I/O I/O
ページ3に含まれる内容の要旨
CY62136EV30 ® MoBL [5,6] DC Input Voltage ............ –0.3V to 3.9V (V + 0.3V) Maximum Ratings CC MAX Output Current into Outputs (LOW) ............................ 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage ......................................... > 2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature ................................–65°C to + 150°C Latch-up Current ...................................................
ページ4に含まれる内容の要旨
CY62136EV30 ® MoBL [8] Thermal Resistance VFBGA TSOP II Parameter Description Test Conditions Package Package Unit Θ Thermal Resistance Still Air, soldered on a 3 × 4.5 inch, two-layer 75 77 °C/W JA [8] (Junction to Ambient) printed circuit board Θ Thermal Resistance 10 13 °C/W JC [8] (Junction to Case) AC Test Loads and Waveforms R1 ALL INPUT PULSES V V CC CC 90% 90% OUTPUT 10% 10% GND R2 30 pF Rise Time = 1 V/ns Fall Time = 1 V/ns INCLUDING Equivalent to: THÉVENIN EQUIVALENT JIG AND R SCOPE
ページ5に含まれる内容の要旨
CY62136EV30 ® MoBL [10, 11, 12, 13] Switching Characteristics Over the Operating Range 45 ns Parameter Description Min. Max. Unit Read Cycle t Read Cycle Time 45 ns RC t Address to Data Valid 45 ns AA t Data Hold from Address Change 10 ns OHA t CE LOW to Data Valid 45 ns ACE t OE LOW to Data Valid 22 ns DOE [11] t OE LOW to LOW Z 5ns LZOE [11, 12] t OE HIGH to High Z 18 ns HZOE [11] t CE LOW to Low Z 10 ns LZCE [11, 12] t CE HIGH to High Z 18 ns HZCE t CE LOW to Power-Up 0 ns PU t CE HIGH to P
ページ6に含まれる内容の要旨
CY62136EV30 ® MoBL [14, 15] Switching Waveforms [14, 15] Read Cycle 1 (Address Transition Controlled) t RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID [15, 16] Read Cycle No. 2 (OE Controlled) ADDRESS t RC CE t PD t t HZCE ACE OE t HZOE t DOE BHE/BLE t LZOE t HZBE t DBE t LZBE HIGH IMPEDANCE HIGH IMPEDANCE DATA OUT DATA VALID t LZCE t PU V I CC CC SUPPLY 50% 50% CURRENT I SB Notes: 14. The device is continuously selected. OE, CE = V , BHE and/or BLE = V . IL IL 15. WE is HIGH
ページ7に含まれる内容の要旨
CY62136EV30 ® MoBL [14, 15] Switching Waveforms (continued) [13, 17, 18] Write Cycle No. 1 (WE Controlled) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE t BW BHE/BLE OE t SD t HD DATA I/O DATA NOTE19 IN t HZOE [13, 17, 18] Write Cycle No. 2 (CE Controlled) t WC ADDRESS t SCE CE t SA t t AW HA t PWE WE t BW BHE/BLE OE t SD t HD DATA DATA I/O IN NOTE 19 t HZOE Notes: 17. Data I/O is high impedance if OE = V . IH 18. If CE goes HIGH simultaneously with WE = V , the output remains in a high-imp
ページ8に含まれる内容の要旨
CY62136EV30 ® MoBL [14, 15] Switching Waveforms (continued) [18] Write Cycle No. 3 (WE Controlled, OE LOW) t WC ADDRESS t SCE CE t BW BHE/BLE t t AW HA t t SA PWE WE t HD t SD NOTE 19 DATAI/O DATA IN t HZWE t LZWE [18] Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) t WC ADDRESS CE t SCE t t AW HA t BW BHE/BLE t SA t PWE WE t HZWE t t HD SD DATA I/O DATA NOTE 19 IN t LZWE Document #: 38-05569 Rev. *B Page 8 of 12 [+] Feedback
ページ9に含まれる内容の要旨
CY62136EV30 ® MoBL Truth Table CE WE OE BHE BLE Inputs/Outputs Mode Power H X X X X High Z Deselect/Power-down Standby (I ) SB L X X H H High Z Output Disabled Active (I ) CC L H L L L Data Out (I/O –I/O ) Read Active (I ) O 15 CC L H L H L Data Out (I/O –I/O ); Read Active (I ) O 7 CC I/O –I/O in High Z 8 15 L H L L H Data Out (I/O –I/O ); Read Active (I ) 8 15 CC I/O –I/O in High Z 0 7 L H H L L High Z Output Disabled Active (I ) CC L H H H L High Z Output Disabled Active (I ) CC L H H L H
ページ10に含まれる内容の要旨
CY62136EV30 ® MoBL Package Diagrams 48-pin VFBGA (6 x 8 x 1 mm) (51-85150) BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 1 2346 5 65 4 3 2 1 A A B B C C D D E E F F G G H H 1.875 A A 0.75 B 6.00±0.10 3.75 B 6.00±0.10 0.15(4X) 51-85150-*D SEATING PLANE C Document #: 38-05569 Rev. *B Page 10 of 12 [+] Feedback 0.25 C 8.00±0.10 0.26 MAX. 0.55 MAX. 0.21±0.05 1.00 MAX 0.10 C 8.00±0.10 5.25 0.75 2.625
ページ11に含まれる内容の要旨
CY62136EV30 ® MoBL Package Diagrams (continued) 44-pin TSOP II (51-85087) 51-85087-*A MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05569 Rev. *B Page 11 of 12 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no respon
ページ12に含まれる内容の要旨
CY62136EV30 ® MoBL Document History Page ® Document Title: CY62136EV30 MoBL 2-Mbit (128K x 16) Static RAM Document Number: 38-05569 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 237432 See ECN AJU New Data Sheet *A 419988 See ECN RXU Converted from Advanced Information to Final. Changed the address of Cypress Semiconductor Corporation on Page #1 from “3901 North First Street” to “198 Champion Court” Removed 35ns Speed Bin Removed “L” version of CY62136EV30 Changed I (Max)
