ページ1に含まれる内容の要旨
PSoC™ Mixed Signal Array Final Data Sheet
CY8C22113 and CY8C22213
Features
■ Powerful Harvard Architecture Processor ■ Precision, Programmable Clocking ■ Additional System Resources
2
❐ M8C Processor Speeds to 24 MHz ❐ Internal ±2.5% 24/48 MHz Oscillator
❐ I C Slave, Master, and Multi-Master to
❐ Low Power at High Speed ❐ High-Accuracy 24 MHz with Optional 32.768
400 kHz
kHz Crystal and PLL
❐ 3.0 to 5.25 V Operating Voltage
❐ Watchdog and Sleep Timers
❐ Optional External Oscillator, up to 24
ページ2に含まれる内容の要旨
Row Output Configuration Digital Clocks From Core CY8C22x13 Final Data Sheet PSoC™ Overview processor. The CPU utilizes an interrupt controller with 10 vec- Digital peripheral configurations include those listed below. tors, to simplify programming of real time embedded events. ■ PWMs (8 to 32 bit) Program execution is timed and protected using the included ■ PWMs with Dead band (8 to 32 bit) Sleep and Watch Dog Timers (WDT). ■ Counters (8 to 32 bit) Memory encompasses 2 KB of Flash for program
ページ3に含まれる内容の要旨
CY8C22x13 Final Data Sheet PSoC™ Overview Analog blocks are provided in columns of three, which includes Additional System Resources one CT (Continuous Time) and two SC (Switched Capacitor) System Resources, some of which have been previously listed, blocks. The number of blocks is dependant on the device family provide additional capability useful to complete systems. Addi- which is detailed in the table titled “PSoC Device Characteris- tional resources include a decimator, low voltage detectio
ページ4に含まれる内容の要旨
Results CY8C22x13 Final Data Sheet PSoC™ Overview Getting Started Development Tools ® The quickest path to understanding the PSoC silicon is by read- The Cypress MicroSystems PSoC Designer is a Microsoft ing this data sheet and using the PSoC Designer Integrated Windows-based, integrated development environment for the Development Environment (IDE). This data sheet is an over- Programmable System-on-Chip (PSoC) devices. The PSoC view of the PSoC integrated circuit and presents specific pin, Desi
ページ5に含まれる内容の要旨
CY8C22x13 Final Data Sheet PSoC™ Overview Debugger PSoC Designer Software Subsystems The PSoC Designer Debugger subsystem provides hardware Device Editor in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC The Device Editor subsystem allows the user to select different device. Debugger commands allow the designer to read and onboard analog and digital components called user modules program and read and write data memor
ページ6に含まれる内容の要旨
CY8C22x13 Final Data Sheet PSoC™ Overview the device to your specification and provides the high-level user User Modules and the PSoC module API functions. Development Process The development process for the PSoC device differs from that Device Editor of a traditional fixed function microprocessor. The configurable Placement analog and digital hardware blocks give the PSoC architecture User Source and a unique flexibility that pays dividends in managing specification Module Code Parameter Sele
ページ7に含まれる内容の要旨
CY8C22x13 Final Data Sheet PSoC™ Overview Document Conventions Table of Contents For an in depth discussion and more information on your PSoC Acronyms Used device, obtain the PSoC Mixed Signal Array Technical Refer- ence Manual. This document encompasses and is organized The following table lists the acronyms that are used in this doc- into the following chapters and sections. ument. 1. Pin Information ............................................................. 8 Acronym Description AC altern
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1. Pin Information This chapter describes, lists, and illustrates the CY8C22x13 PSoC device pins and pinout configurations. 1.1 Pinouts The CY8C22x13 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO. 1.1.1 8-Pin Part Pinout Table 1-1. 8-Pin Part Pinout (PDIP, SOIC) Type CY8C22113 8-Pin PSoC Device Pin Pin Descr
ページ9に含まれる内容の要旨
CY8C22x13 Final Data Sheet 1. Pin Information 1.1.3 32-Pin Part Pinout Table 1-3. 32-Pin Part Pinout (MLF*) Type CY8C22213 PSoC Device Pin Pin Description No. Name Digital Analog 1 NC No connection. Do not use. 2 NC No connection. Do not use. 3 NC No connection. Do not use. 4 NC No connection. Do not use. 5 Power Vss Ground connection. NC 1 24 P0[2], AI 6 Power Vss Ground connection. NC 2 P0[0], AI 23 7 IO P1[7] I2C Serial Clock (SCL) NC 3 22 NC 8 IO P1[5] I2C Serial Data (SDA) NC 4 21 NC ML
ページ10に含まれる内容の要旨
2. Register Reference This chapter lists the registers of the CY8C22x13 PSoC device by way of mapping tables, in offset order. For detailed register infor- mation, reference the PSoC™ Mixed Signal Array Technical Reference Manual. 2.1 Register Conventions 2.2 Register Mapping Tables The PSoC device has a total register address space of 512 2.1.1 Abbreviations Used bytes. The register space is also referred to as IO space and is broken into two parts. The XOI bit in the Flag register deter- The r
ページ11に含まれる内容の要旨
Access Addr (0,Hex) Name Access Addr (0,Hex) Name Access Addr (0,Hex) Name Access Addr (0,Hex) Name CY8C22x13 Final Data Sheet 2. Register Reference Register Map Bank 0 Table: User Space PRT0DR 00 RW 40 80 C0 PRT0IE 01 RW 41 81 C1 PRT0GS 02 RW 42 82 C2 PRT0DM2 03 RW 43 83 C3 PRT1DR 04 RW 44 ASD11CR0 84 RW C4 PRT1IE 05 RW 45 ASD11CR1 85 RW C5 PRT1GS 06 RW 46 ASD11CR2 86 RW C6 PRT1DM2 07 RW 47 ASD11CR3 87 RW C7 08 48 88 C8 09 49 89 C9 0A 4A 8A CA 0B 4B 8B CB 0C 4C 8C CC 0D 4D 8D CD 0E 4E 8E
ページ12に含まれる内容の要旨
Access Addr (1,Hex) Name Access Addr (1,Hex) Name Access Addr (1,Hex) Name Access Addr (1,Hex) Name CY8C22x13 Final Data Sheet 2. Register Reference Register Map Bank 1 Table: Configuration Space PRT0DM0 00 RW 40 80 C0 PRT0DM1 01 RW 41 81 C1 PRT0IC0 02 RW 42 82 C2 PRT0IC1 03 RW 43 83 C3 PRT1DM0 04 RW 44 ASD11CR0 84 RW C4 PRT1DM1 05 RW 45 ASD11CR1 85 RW C5 PRT1IC0 06 RW 46 ASD11CR2 86 RW C6 PRT1IC1 07 RW 47 ASD11CR3 87 RW C7 08 48 88 C8 09 49 89 C9 0A 4A 8A CA 0B 4B 8B CB 0C 4C 8C CC 0D 4D 8D
ページ13に含まれる内容の要旨
Vdd Voltage Valid ating Oper egion R 3. Electrical Specifications This chapter presents the DC and AC electrical specifications of the CY8C22x13 PSoC device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by referencing the web at http://www.cypress.com/psoc. o o o Specifications are valid for -40 C ≤ T ≤ 85 C and T ≤ 100 C as specified, except where noted. Specifications for devices running A J o o o at greater than 12 MHz are valid for -40 C
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CY8C22x13 Final Data Sheet 3. Electrical Specifications 3.1 Absolute Maximum Ratings Table 3-2. Absolute Maximum Ratings Symbol Description Min Typ Max Units Notes o T Storage Temperature -55 – +100 Higher storage temperatures will reduce data STG C retention time. o T Ambient Temperature with Power Applied -40 – +85 A C Vdd Supply Voltage on Vdd Relative to Vss -0.5 – +6.0 V V DC Input Voltage Vss - 0.5 – Vdd + 0.5 V IO – DC Voltage Applied to Tri-state Vss - 0.5 – Vdd + 0.5 V I Maximum Cur
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CY8C22x13 Final Data Sheet 3. Electrical Specifications 3.3 DC Electrical Characteristics 3.3.1 DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and A A are for design guidance only or unless otherwise specified. Table 3-4. DC Chip-Level Specifications Symbol Descrip
ページ16に含まれる内容の要旨
CY8C22x13 Final Data Sheet 3. Electrical Specifications 3.3.3 DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and A A are for design guidance only or unless otherwise specified. The Operational Amplifier is a component of both the Analog Continuous Time PSoC
ページ17に含まれる内容の要旨
CY8C22x13 Final Data Sheet 3. Electrical Specifications Table 3-7. 3.3V DC Operational Amplifier Specifications Symbol Description Min Typ Max Units Notes V Input Offset Voltage (absolute value) Low Power – 1.65 10 mV OSOA Input Offset Voltage (absolute value) Mid Power – 1.32 8 mV High Power is 5 Volt Only o TCV Average Input Offset Voltage Drift – 7.0 35.0 OSOA µV/ C I Input Leakage Current (Port 0 Analog Pins) – 20 – pA Gross tested to 1 µA. EBOA o C Input Capacitance (Port 0 Analog Pins)
ページ18に含まれる内容の要旨
CY8C22x13 Final Data Sheet 3. Electrical Specifications 3.3.4 DC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and A A are for design guidance only or unless otherwise specified. Table 3-8. 5V DC Analog Output Buffer Specifications Symbol Description Min Typ
ページ19に含まれる内容の要旨
CY8C22x13 Final Data Sheet 3. Electrical Specifications 3.3.5 DC Analog Reference Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and A A are for design guidance only or unless otherwise specified. The guaranteed specifications are measured through the Analog Continuous Time PSoC bl
ページ20に含まれる内容の要旨
CY8C22x13 Final Data Sheet 3. Electrical Specifications 3.3.7 DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ T ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and A A are for design guidance only or unless otherwise specified. Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See
