ページ1に含まれる内容の要旨
PRELIMINARY CY8CNP102B, CY8CNP102E
Nonvolatile Programmable System-on-Chip
(PSoC® NV)
■ Precision, Programmable Clocking
Overview
❐ Internal ±2.5% 24 and 48 MHz Oscillator
The Cypress nonvolatile Programmable System-on-Chip
❐ 24 and 48 MHz with optional 32.768 kHz Crystal
®
(PSoC NV) processor combines a versatile Programmable
❐ Optional External Oscillator, up to 24 MHz
System-on-Chip™ (PSoC) core with an infinite endurance
❐ Internal Oscillator for Watchdog and Sleep
nvSRAM in a single package
ページ2に含まれる内容の要旨
PRELIMINARY CY8CNP102B, CY8CNP102E Logic Block Diagram Document #: 001-43991 Rev. *D Page 2 of 38 [+] Feedback
ページ3に含まれる内容の要旨
PRELIMINARY CY8CNP102B, CY8CNP102E Pinouts Figure 1. Pin Diagram - 100-Pin TQFP Package (14 x 14 x 1.4 mm) Table 1. Pin Definitions - 100-Pin TQFP Type Pin Number Pin Name Pin Definition Digital Analog 1 P0_5 IO IO Analog Column Mux Input and Column Output 2 P0_3 IO IO Analog Column Mux Input and Column Output 3 P0_1 IO I Analog Column Mux Input, GPIO 4P2_7 IO GPIO 5P2_5 IO GPIO 6 P2_3 IO I Direct Switched Capacitor Block Input 7 P2_1 IO I Direct Switched Capacitor Block Input 8 Vcc Power Su
ページ4に含まれる内容の要旨
PRELIMINARY CY8CNP102B, CY8CNP102E Table 1. Pin Definitions - 100-Pin TQFP (continued) Type Pin Number Pin Name Pin Definition Digital Analog 18 P5_7 IO GPIO 19 P5_5 IO GPIO 20 P5_3 IO GPIO 21 P5_1 IO GPIO 22 P1_7 IO I2C Serial Clock (SCL), GPIO 23 P1_5 IO I2C Serial Data (SDA), GPIO 24 P1_3 IO GPIO 25 P1_1 IO Serial Clock (SCL), Crystal (XTALin), GPIO 26 NV_W Connect to pin 16 (NV_W to EN_W) 27 - 34 NC Not connected on the die 35 - 39 Vss Power Ground 40 - 47 NC Not connected on the die 48
ページ5に含まれる内容の要旨
PRELIMINARY CY8CNP102B, CY8CNP102E Table 1. Pin Definitions - 100-Pin TQFP (continued) Type Pin Number Pin Name Pin Definition Digital Analog 79 HSB# Weak Pull up. Connect 10kΩ to Vcc. 80 Vcc Power Supply Voltage 81 - 85 NC Not connected on the die 86 - 90 Vss Power Ground 91 - 98 NC Not connected on the die 99 NV_C Connect to Pin 61 (NV_C to EN_C).Weak Pull up. Connect 10kΩ to Vcc. 100 P0_7 IO I Analog Column Mux Input, GPIO interfacing. Every pin also has the capability to generate a PSo
ページ6に含まれる内容の要旨
PRELIMINARY CY8CNP102B, CY8CNP102E ■ Peak Detectors Programmable Digital System ■ Other possible topologies The digital system contains 16 digital PSoC blocks. Each block is an 8-bit resource that is used alone or combined with other ■ Analog blocks are provided in columns of three, which includes blocks to form 8, 16, 24, and 32-bit peripherals, which are called one CT (Continuous Time) and two SC (Switched Capacitor) user module references. The digital peripheral configurations blocks. are: Ad
ページ7に含まれる内容の要旨
Results PRELIMINARY CY8CNP102B, CY8CNP102E Development Tools PSoC Designer Software Subsystems ® PSoC Designer is a Microsoft Windows based, integrated Device Editor development environment for Programmable System-on-Chip The Device Editor subsystem enables the user to select different (PSoC) devices. The PSoC Designer IDE and application run on onboard analog and digital components called user modules, Windows NT 4.0, Windows 2000, Windows Millennium (Me), using the PSoC blocks. Examples of use
ページ8に含まれる内容の要旨
PRELIMINARY CY8CNP102B, CY8CNP102E Online Help System The development process starts when you open a new project and bring up the Device Editor, which is a graphical user The online help system displays online, context sensitive help for interface (GUI) for configuring the hardware. Pick the user the user. Designed for procedural and quick reference, each modules required for your project and map them onto the PSoC functional subsystem has its own context sensitive help. This blocks with point a
ページ9に含まれる内容の要旨
Vdd Voltage Vdd Voltage Region PRELIMINARY CY8CNP102B, CY8CNP102E The last step in the development process takes place inside the Cypress nvSRAM user Module PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where The nvSRAM user module is integrated with the PSoC Designer it runs at full speed. The Debugger capabilities rival those of tool and contains APIs that facilitate nvSRAM access and systems costing much more. In addition to traditio
ページ10に含まれる内容の要旨
PRELIMINARY CY8CNP102B, CY8CNP102E 3.3V Operation Absolute Maximum Ratings Table 3. 3.3V Absolute Maximum Ratings (CY8CNP102B) Symbol Description Min Typ Max Units Notes o T Storage Temperature -55 25 +100 C Higher storage temperatures STG reduce data retention time. Recommended storage o temperature is ± 25 C. Extended duration storage o temperatures above 65 C degrade reliability. o T Ambient Temperature with Power Applied -40 – +85 C A Vcc Supply Voltage on Vcc Relative to Vss -0.5 – +
ページ11に含まれる内容の要旨
PRELIMINARY CY8CNP102B, CY8CNP102E DC Electrical Characteristics The following DC electrical specifications list the guaranteed maximum and minimum specifications for the voltage and temperature range: 3.0V to 3.6V over the Temperature range of -40°C ≤ T ≤ 85°C. Typical parameters apply to 3.3V at 25°C and are for design A guidance only. DC Chip Level Specifications Table 5. 3.3V DC Chip Level Specifications (CY8CNP102B) Symbol Description Min Typ Max Units Notes Vcc Supply Voltage 3.00 – 3.6 V
ページ12に含まれる内容の要旨
PRELIMINARY CY8CNP102B, CY8CNP102E DC Operational Amplifier Specifications The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Table 7. 3.3V DC Operational Amplifier Specifications (CY8CNP102B) Symbol Description Min Typ Max Units Notes V Input Offset Voltage (absolute value) High Power is 5 Volts Only OSOA Power = Low, Opamp B
ページ13に含まれる内容の要旨
PRELIMINARY CY8CNP102B, CY8CNP102E DC Analog Output Buffer Specifications Table 9. 3.3V DC Analog Output Buffer Specifications (CY8CNP102B) Symbol Description Min Typ Max Units V Input Offset Voltage (Absolute Value) – 3 12 mV OSOB TCV Average Input Offset Voltage Drift – +6 – μV/°C OSOB V Common-Mode Input Voltage Range 0.5 - Vcc - 1.0 V CMOB R Output Resistance OUTOB Power = Low – – 10 Ω Power = High – – 10 Ω V High Output Voltage Swing OHIGHOB (Load = 1KΩ to Vcc/2) Power = Low 0.5 x Vcc
ページ14に含まれる内容の要旨
PRELIMINARY CY8CNP102B, CY8CNP102E DC Analog Reference Specifications The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Table 10. 3.3
ページ15に含まれる内容の要旨
PRELIMINARY CY8CNP102B, CY8CNP102E DC POR, SMP, and LVD Specifications Table 12. 3.3V DC POR, SMP, and LVD Specifications (CY8CNP102B) Symbol Description Min Typ Max Units Vdd Value for PPOR Trip (positive ramp) V PORLEV[1:0] = 00b 2.91 V PPOR0R Vdd Value for PPOR Trip (negative ramp) V PORLEV[1:0] = 00b 2.82 V PPOR0 PPOR Hysteresis V PORLEV[1:0] = 00b 92 mV PH0 V PORLEV[1:0] = 01b 0 mV PH1 V PORLEV[1:0] = 10b 0 mV PH2 Vdd Value for LVD Trip [2] V VM[2:0] = 000b 2.86 2.92 2.98 V LVD0 V VM[2:0]
ページ16に含まれる内容の要旨
PRELIMINARY CY8CNP102B, CY8CNP102E DC Programming Specifications Table 13. 3.3V DC Programming Specifications (CY8CNP102B) Symbol Description Min Typ Max Units Notes I Supply Current During Programming or Verify – 10 30 mA DDPV V Input Low Voltage During Programming or Verify – – 0.8 V ILP V Input High Voltage During Programming or Verify 2.2 – – V IHP I Input Current when Applying Vilp to P1[0] or P1[1] – – 0.2 mA Driving internal pull ILP During Programming or Verify down resistor. I Input C
ページ17に含まれる内容の要旨
PRELIMINARY CY8CNP102B, CY8CNP102E AC Electrical Characteristics The following AC electrical specifications list the guaranteed maximum and minimum specifications for the voltage and temperature range: 3.0V to 3.6V over the temperature range of -40°C ≤ T ≤ 85°C. Typical parameters apply to 3.3V at 25°C and are for design A guidance only. AC Chip Level Specifications Table 14. 3.3V AC Chip Level Specifications (CY8CNP102B) Symbol Description Min Typ Max Units Notes [4, 5, 6] F Internal Main Osci
ページ18に含まれる内容の要旨
PRELIMINARY CY8CNP102B, CY8CNP102E In the following table, t starts from the time Vcc rises above V If an SRAM WRITE has not taken place since the last HRECALL SWITCH. nonvolatile cycle, no STORE occurs. Industrial grade devices require 15 ms maximum. Table 15.3.3V nvSRAM AutoStore/Power Up RECALL (CY8CNP102B) nvSRAM Parameter Description Unit Min Max t Power Up RECALL Duration 20 ms HRECALL t STORE Cycle Duration 12.5 ms STORE V Low Voltage Trigger Level 2.65 V SWITCH t VCC Rise Time 150 μs
ページ19に含まれる内容の要旨
PRELIMINARY CY8CNP102B, CY8CNP102E AC Operational Amplifier Specifications Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Table 17. 3.3V AC Operational Amplifier Specifications (CY8CNP102B) Symbol Description Min Typ Max Units Notes T Rising Settling Time to 0.1% of a 1V Step Power = High and ROA (10 pF load, Unity Gain) Opamp Bias = High is not supported at Power = Low, Opamp Bias = Low – – 3.92 μs 3.3V. Power = Medium, Opamp Bias = High
ページ20に含まれる内容の要旨
PRELIMINARY CY8CNP102B, CY8CNP102E Table 18. 3.3V AC Digital Block Specifications (CY8CNP102B) (continued) Function Description Min Typ Max Units Notes CRCPRS Maximum Input Clock Frequency – – 24.6 MHz 3.0V ≤ Vcc ≤ 3.6V (PRS Mode) CRCPRS Maximum Input Clock Frequency – – 24.6 MHz 3.0V ≤ Vcc ≤ 3.6V. (CRC Mode) SPIM Maximum Input Clock Frequency – – 8.2 MHz Maximum data rate at 4.1 MHz due to 2 x over clocking. SPIS Maximum Input Clock Frequency – – 4.1 ns [8] Width of SS_ Negated Between Trans
