ページ1に含まれる内容の要旨
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
36-Mbit (1M x 36/2M x 18/512K x 72)
Pipelined SRAM with NoBL™ Architecture
Features Functional Description
• Pin-compatible and functionally equivalent to ZBT™ The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are
3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst
• Supports 250-MHz bus operations with zero wait states
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.
— Available speed grades are 250, 200 and 167 MHz
They are designed to support un
ページ2に含まれる内容の要旨
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Logic Block Diagram-CY7C1462AV33 (2M x 18) ADDRESS A0, A1, A REGISTER 0 A1 A1' D1 Q1 A0 BURST A0' D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O U U T T P S P D U E A U ADV/LD T N T T WRITE REGISTRY S A R MEMORY E B AND DATA COHERENCY BWa WRITE E DQs U ARRAY S CONTROL LOGIC G DRIVERS A T F DQPa I M F BWb E S DQPb P E E T S R R E I S R N WE S G E E INPUT INPUT E E REGISTER 1 REGISTER 0 OE READ LOGIC CE1 CE2 CE3
ページ3に含まれる内容の要旨
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Pin Configurations 100-pin TQFP Pinout DQPc 1 NC 1 A DQPb 80 80 DQc 2 NC 2 DQb NC 79 79 DQc 3 DQb NC 3 NC 78 78 V DDQ 4 V 4 V DDQ 77 DDQ V 77 DDQ V 5 V V 5 SS SS V 76 SS SS 76 DQc 6 NC 6 DQb NC 75 75 DQc 7 DQb NC 7 DQPa 74 74 DQc 8 DQb DQb 8 DQa 73 73 DQc 9 DQb DQb 9 DQa 72 72 V V SS 10 V SS SS 10 V 71 SS 71 V V DDQ 11 DDQ V 11 V 70 DDQ 70 DDQ DQc 12 DQb DQb 12 DQa 69 69 DQc 13 DQb DQb 13 DQa 68 68 NC NC 14 V 14 V 67 SS CY7C1462AV33 CY7C1460AV33 67 SS
ページ4に含まれる内容の要旨
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1460AV33 (1M × 36) 1 2 3 4 567 89 10 11 A ADV/LD A A A NC/576M CE BW BW CE NC CEN 1 c b 3 NC/1G CE2 WE OE A NC B A BW BW CLK A d a C DQP NC V V V V V V V NC DQP c DDQ SS SS SS SS SS DDQ b D DQ DQ V V V V V V V DQ DQ c c DDQ DD SS SS SS DD DDQ b b DQ V V V V DQ DQ E DQ V V V c c DDQ DD SS SS SS DD DDQ b b F DQ DQ V V V V V V V DQ DQ c c DDQ DD SS SS SS DD DDQ b b G DQ DQ V V V V V
ページ5に含まれる内容の要旨
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Pin Configurations (continued) 209-ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1464AV33 (512K x 72) 12 3456789 10 11 DQg A DQg CE DQb CE ADV/LD DQb 3 AA 2 A A DQg B DQg A BWS NC DQb BWS BWS WE b BWS DQb c g f DQg C DQg NC/576M NC BWS CE BWS BWS DQb BWS DQb d 1 e a h D DQg DQg NC NC V NC/1G OE V NC DQb SS SS DQb E DQPg DQPc V V V V V V V DDQ DDQ DD DD DD DDQ DDQ DQPf DQPb DQc F DQc V V V NC V V DQf V SS SS SS SS SS DQf SS G DQc DQc V V V V V V DDQ DDQ NC DD D
ページ6に含まれる内容の要旨
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Pin Definitions (continued) Pin Name I/O Type Pin Description CLK Input- Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with Clock CEN. CLK is only recognized if CEN is active LOW. CE Input- Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction 1 Synchronous with CE and CE to select/deselect the device. 2 3 CE Input- Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK
ページ7に含まれる内容の要旨
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Functional Overview the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are cycle. Therefore, the type of access (Read or Write) is synchronous-pipelined Burst NoBL SRAMs designed specifi- maintained throughout the burst sequence. cally to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers
ページ8に含まれる内容の要旨
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 counter is incremented. The correct BW (BW for a,b,c,d,e,f,g,h Interleaved Burst Address Table CY7C1464AV33, BW for CY7C1460AV33 and BW for a,b,c,d a,b (MODE = Floating or V ) DD CY7C1462AV33) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. First Second Third Fourth Address Address Address Address Sleep Mode A1,A0 A1,A0 A1,A0 A1,A0 The ZZ input pin is an asynchronous input. Asserting ZZ 00 01 10 11
ページ9に含まれる内容の要旨
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 [1, 2, 3, 4, 5, 6, 7] Truth Table (continued) Address Operation Used CE ZZ ADV/LD WE BW OE CEN CLK DQ x Write Cycle External L L L L L X L L-H Data In (D) (Begin Burst) Write Cycle Next X L H X L X L L-H Data In (D) (Continue Burst) NOP/WRITE ABORT None L L L L H X L L-H Tri-State (Begin Burst) WRITE ABORT Next X L H X H X L L-H Tri-State (Continue Burst) IGNORE CLOCK Current X L X X X X H L-H - EDGE (Stall) SLEEP MODE None X H X X X X X X Tri-State [1,
ページ10に含まれる内容の要旨
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Test Data-In (TDI) IEEE 1149.1 Serial Boundary Scan (JTAG) The TDI ball is used to serially input information into the The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 incor- registers and can be connected to the input of any of the porates a serial boundary scan test access port (TAP). This registers. The register between TDI and TDO is chosen by the part is fully compliant with 1149.1. The TAP operates using instruction that is loaded into the TAP instruction
ページ11に含まれる内容の要旨
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 When the TAP controller is in the Capture-IR state, the two SAMPLE Z least significant bits are loaded with a binary “01” pattern to The SAMPLE Z instruction causes the boundary scan register allow for fault isolation of the board-level serial test data path. to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts Bypass Register the output bus into a High-Z state until the next command is To
ページ12に含まれる内容の要旨
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 When this scan cell, called the “extest output bus tri-state,” is loaded into that shift-register cell will latch into the preload latched into the preload register during the “Update-DR” state register. When the EXTEST instruction is entered, this bit will in the TAP controller, it will directly control the state of the directly control the output Q-bus pins. Note that this bit is output (Q-bus) pins, when the EXTEST is entered as the preset HIGH to enab
ページ13に含まれる内容の要旨
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ................................................ V to 3.3V Input pulse levels ................................................V to 2.5V SS SS Input rise and fall times................................................... 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels...........................................1.5V
ページ14に含まれる内容の要旨
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Scan Register Sizes Register Name Bit Size (×36) Bit Size (×18) Bit Size (×72) Instruction 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order (165-ball FBGA package) 89 89 - Boundary Scan Order (209-ball FBGA package) - - 138 Identification Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. IDCODE 001 Loads the ID register with the vendo
ページ15に含まれる内容の要旨
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 [13] 165-ball FBGA Boundary Scan Order CY7C1460AV33 (1M x 36), CY7C1462AV33 (2M x 18) Bit# ball ID Bit# ball ID Bit# ball ID Bit# ball ID 1N6 26 E11 51 A3 76 N1 2N7 27 D11 52 A2 77 N2 3 10N 28 G10 53 B2 78 P1 4P11 29 F10 54 C2 79 R1 5 P8 30 E10 55 B1 80 R2 6 R8 31 D10 56 A1 81 P3 7 R9 32 C11 57 C1 82 R3 8P9 33 A11 58 D1 83 P2 9P10 34 B11 59E1 84 R4 10 R10 35 A10 60 F1 85 P4 11 R11 36 B10 61 G1 86 N5 12 H11 37 A9 62 D2 87 P6 13 N11 38 B9 63 E2 88 R6 14 M11
ページ16に含まれる内容の要旨
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 [13, 14] 209-ball BGA Boundary Scan Order CY7C14604V33 (512K x 72) Bit# Ball ID Bit# ball ID Bit# ball ID Bit# ball ID 1 36 6F 71 6H 106 3K W6 2 37 8K 72 6C 107 4K V6 3 U6 38 9K 73 6B 108 6K 4 W7 39 10K 74 6A 109 2K 5 V7 40 11J 75 5A 110 2L 6 U7 41 10J 76 5B 111 1L 7 T7 42 11H 77 5C 112 2 Mbit 8 V8 43 10H 78 5D 113 1 Mbit 9 U8 44 11G 79 4D 114 2N 10 T8 45 10G 80 4C 115 1N 11 V9 46 11F 81 4A 116 2P 12 U9 47 10F 82 4B 117 1P 13 P6 48 10E 83 3C 118 2R 14 W11
ページ17に含まれる内容の要旨
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Current into Outputs (LOW)......................................... 20 mA Maximum Ratings Static Discharge Voltage.......................................... > 2001V (Above which the useful life may be impaired. For user guide- (per MIL-STD-883, Method 3015) lines, not tested.) Latch-up Current.................................................... > 200 mA Storage Temperature .................................–65°C to +150°C Operating Range Ambient Temperat
ページ18に含まれる内容の要旨
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 [17] Capacitance 100 TQFP 165 FBGA 209 FBGA Parameter Description Test Conditions Max. Max. Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 6.5 7 5 pF IN A V = 2.5V V = 2.5V DD DDQ C Clock Input Capacitance 3 7 5 pF CLK C Input/Output Capacitance 5.5 6 7 pF I/O [17] Thermal Resistance 100 TQFP 165 FBGA 209 FBGA Parameters Description Test Conditions Package Package Package Unit Θ Thermal Resistance Test conditions follow standard 25.21 20.8 25.31 °
ページ19に含まれる内容の要旨
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 [22, 23] Switching Characteristics Over the Operating Range –250 –200 –167 Parameter Description Min. Max. Min. Max. Min. Max. Unit [18] t V (typical) to the first access read or write 1 1 1 ms Power CC Clock t Clock Cycle Time 4.0 5.0 6.0 ns CYC F Maximum Operating Frequency 250 200 167 MHz MAX t Clock HIGH 1.5 2.0 2.4 ns CH t Clock LOW 1.5 2.0 2.4 ns CL Output Times t Data Output Valid After CLK Rise 2.6 3.2 3.4 ns CO t OE LOW to Output Valid 2.6 3.0 3.
ページ20に含まれる内容の要旨
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Switching Waveforms [24, 25, 26] Read/Write/Timing 123 456789 10 t CYC CLK t t t t CENS CENH CL CH CEN t t CES CEH CE ADV/LD WE BWx A1 A2 ADDRESS A3 A4 A5 A6 A7 t CO t t DS DH t t t t DOH t t CLZ OEV CHZ AS AH Data D(A1) D(A2) D(A2+1) Q(A3) Q(A4) Q(A4+1) D(A5) Q(A6) In-Out (DQ) t OEHZ t DOH t OELZ OE WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELECT D(A1) D(A2) WRITE Q(A3) Q(A4) READ D(A5) Q(A6) D(A7) D(A2+1) Q(A4+1) DON’T CARE UNDEFINED Notes
