ページ1に含まれる内容の要旨
CY7C1511JV18, CY7C1526JV18
CY7C1513JV18, CY7C1515JV18
72-Mbit QDR™-II SRAM 4-Word
Burst Architecture
Features Configurations
■ Separate independent read and write data ports CY7C1511JV18 – 8M x 8
❐ Supports concurrent transactions CY7C1526JV18 – 8M x 9
CY7C1513JV18 – 4M x 18
■ 300 MHz clock for high bandwidth
CY7C1515JV18 – 2M x 36
■ 4-word burst for reducing address bus frequency
Functional Description
■ Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 600 M
ページ2に含まれる内容の要旨
2M x 8 Array 2M x 9 Array 2M x 8 Array 2M x 9 Array 2M x 8 Array 2M x 9 Array 2M x 8 Array 2M x 9 Array CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Logic Block Diagram (CY7C1511JV18) 8 D [7:0] Write Write Write Write 21 Address A Reg Reg Reg Reg (20:0) Register 21 Address A (20:0) Register RPS K Control CLK K Logic Gen. C DOFF Read Data Reg. C CQ 32 V 16 REF 8 CQ Reg. Reg. Control WPS 8 Logic 8 8 16 NWS Q Reg. [1:0] [7:0] 8 Logic Block Diagram (CY7C1526JV18) 9 D [8:0] Write Write Write
ページ3に含まれる内容の要旨
1M x 18 Array 512K x 36 Array 1M x 18 Array 512K x 36 Array 1M x 18 Array 512K x 36 Array 1M x 18 Array 512K x 36 Array CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Logic Block Diagram (CY7C1513JV18) 18 D [17:0] Write Write Write Write 20 Address A Reg Reg Reg Reg (19:0) Register 20 Address A (19:0) Register RPS K Control CLK K Logic Gen. C DOFF Read Data Reg. C CQ 72 V 36 REF CQ 18 Reg. Reg. Control 18 WPS Logic 18 18 36 BWS Q Reg. [17:0] [1:0] 18 Logic Block Diagram (CY7C1515JV18) 36
ページ4に含まれる内容の要旨
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Pin Configuration [1] The pin configuration for CY7C1511JV18, CY7C1513JV18, and CY7C1515JV18 follow. 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1511JV18 (8M x 8) 123456789 10 11 A CQ AA WPS NWS K NC/144M RPS AA CQ 1 B NC NC NC A NC/288M K NWS ANC NC Q3 0 C NC NC NC V ANC A V NC NC D3 SS SS D NC D4 NC V V V V V NC NC NC SS SS SS SS SS E NC NC Q4 V V V V V NC D2 Q2 DDQ SS SS SS DDQ F NC NC NC V V V V V NC NC NC DDQ DD SS DD DDQ G NC D5 Q5 V
ページ5に含まれる内容の要旨
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Pin Configuration [1] The pin configuration for CY7C1511JV18, CY7C1513JV18, and CY7C1515JV18 follow. (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1513JV18 (4M x 18) 123456789 10 11 A CQ NC/144M A WPS BWS K NC/288M RPS AA CQ 1 B NC Q9 D9 A NC K BWS ANC NC Q8 0 C NC NC D10 V ANC A V NC Q7 D8 SS SS D NC D11 Q10 V V V V V NC NC D7 SS SS SS SS SS E NC NC Q11 V V V V V NC D6 Q6 DDQ SS SS SS DDQ F NC Q12 D12 V V V V V NC NC Q5 DDQ DD SS
ページ6に含まれる内容の要旨
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Pin Definitions Pin Name IO Pin Description D Input- Data Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active. [x:0] Synchronous CY7C1511JV18 − D [7:0] CY7C1526JV18 − D [8:0] CY7C1513JV18 − D [17:0] CY7C1515JV18 − D [35:0] WPS Input- Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a Synchronous write operation is initiated. Deasserting deselects
ページ7に含まれる内容の要旨
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Pin Definitions (continued) Pin Name IO Pin Description CQ Echo Clock CQ is Referenced with Respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the Switching Characteristics on page 23. CQ Echo Clock CQ is Referenced with Respect to C. This is a free running clock and is
ページ8に含まれる内容の要旨
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 initiated on two consecutive K clock rises. The internal logic of Functional Overview the device ignores the second read request. Read accesses can The CY7C1511JV18, CY7C1526JV18, CY7C1513JV18, be initiated on every other K clock rise. Doing so pipelines the CY7C1515JV18 are synchronous pipelined Burst SRAMs with a data flow such that data is transferred out of the device on every read port and a write port. The read port is dedicated to read
ページ9に含まれる内容の要旨
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Concurrent Transactions Programmable Impedance The read and write ports on the CY7C1513JV18 operates An external resistor, RQ, must be connected between the ZQ pin completely independently of one another. As each port latches on the SRAM and V to allow the SRAM to adjust its output SS the address inputs on different clock edges, the user can read or driver impedance. The value of RQ must be 5X the value of the write to any location, regardle
ページ10に含まれる内容の要旨
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Application Example Figure 1 shows four QDR-II used in an application. Figure 1. Application Example SRAM #1 R = 250ohms SRAM #4 R = 250ohms ZQ ZQ R W B R W B CQ/CQ# CQ/CQ# Vt P P W P P W D Q D Q S S S S S S R A # CC# K K# # # A # # # CC# K K# DATA IN DATA OUT Vt Address Vt R RPS# BUS WPS# MASTER BWS# (CPU CLKIN/CLKIN# or Source K ASIC) Source K# Delayed K Delayed K# R R = 50ohms Vt = Vddq/2 Truth Table [2, 3, 4, 5, 6, 7] The truth table for
ページ11に含まれる内容の要旨
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Write Cycle Descriptions [2, 10] The write cycle description table for CY7C1511JV18 and CY7C1513JV18 follows. BWS / BWS / 0 1 K Comments K NWS NWS 0 1 L L L–H – During the data portion of a write sequence: CY7C1511JV18 − both nibbles (D ) are written into the device. [7:0] CY7C1513JV18 − both bytes (D ) are written into the device. [17:0] L L – L-H During the data portion of a write sequence: CY7C1511JV18 − both nibbles (D ) are written i
ページ12に含まれる内容の要旨
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Write Cycle Descriptions [2, 10] The write cycle description table for CY7C1515JV18 follows. BWS BWS BWS BWS K K Comments 0 1 2 3 LLLL L–H – During the Data portion of a write sequence, all four bytes (D ) are written into [35:0] the device. LLLL – L–H During the Data portion of a write sequence, all four bytes (D ) are written into [35:0] the device. L H H H L–H – During the Data portion of a write sequence, only the lower byte (D ) is w
ページ13に含まれる内容の要旨
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Instruction Register IEEE 1149.1 Serial Boundary Scan (JTAG) Three-bit instructions can be serially loaded into the instruction These SRAMs incorporate a serial boundary scan Test Access register. This register is loaded when it is placed between the TDI Port (TAP) in the FBGA package. This part is fully compliant with and TDO pins, as shown in TAP Controller Block Diagram on IEEE Standard #1149.1-2001. The TAP operates using JEDEC page 16. U
ページ14に含まれる内容の要旨
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 IDCODE PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection The IDCODE instruction loads a vendor-specific, 32-bit code into of another boundary scan test operation. the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the The shifting of data for the SAMPLE and PRELOAD phases can device when the TA
ページ15に含まれる内容の要旨
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 TAP Controller State Diagram [11] The state diagram for the TAP controller follows. TEST-LOGIC 1 RESET 0 1 1 1 TEST-LOGIC/ SELECT SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 0 0 SHIFT-DR SHIFT-IR 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 0 0 PAUSE-DR PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 1 0 0 Note 11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-12560 R
ページ16に含まれる内容の要旨
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 TAP Controller Block Diagram 0 Bypass Register 2 1 0 Selection Selection TDI TDO Instruction Register Circuitry Circuitry 31 30 29 . . 2 1 0 Identification Register . 108 . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics [12, 13, 14] Over the Operating Range Parameter Description Test Conditions Min Max Unit V Output HIGH Voltage I = −2.0 mA 1.4 V OH1 OH Output HIGH Voltage I = −100 μA1.6 V V OH2 OH
ページ17に含まれる内容の要旨
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 TAP AC Switching Characteristics [15, 16] Over the Operating Range Parameter Description Min Max Unit t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH 20 ns TH t TCK Clock LOW 20 ns TL Setup Times t TMS Setup to TCK Clock Rise 5 ns TMSS t TDI Setup to TCK Clock Rise 5 ns TDIS t Capture Setup to TCK Rise 5 ns CS Hold Times t TMS Hold after TCK Clock Rise 5 ns TMSH t TDI Hold after Clock Rise 5 ns TDIH t Capt
ページ18に含まれる内容の要旨
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Identification Register Definitions Value Instruction Field Description CY7C1511JV18 CY7C1526JV18 CY7C1513JV18 CY7C1515JV18 Revision Number 001 001 001 001 Version number. (31:29) Cypress Device ID 11010011011000100 11010011011001100 11010011011010100 11010011011100100 Defines the type of (28:12) SRAM. Cypress JEDEC ID 00000110100 00000110100 00000110100 00000110100 Allows unique (11:1) identification of SRAM vendor. ID Register 1111 Indi
ページ19に含まれる内容の要旨
CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P29 9G 57 5B85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N32 9F 60 5C88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43
ページ20に含まれる内容の要旨
~ ~ CY7C1511JV18, CY7C1526JV18 CY7C1513JV18, CY7C1515JV18 DLL Constraints Power Up Sequence in QDR-II SRAM ■ DLL uses K clock as its synchronizing input. The input must QDR-II SRAMs must be powered up and initialized in a have low phase jitter, which is specified as t . KC Var predefined manner to prevent undefined operations. During Power Up, when the DOFF is tied HIGH, the DLL gets locked ■ The DLL functions at frequencies down to 120 MHz. after 1024 cycles of stable clock. ■ If the input clo
