ページ1に含まれる内容の要旨
CY7C1364C
9-Mbit (256K x 32) Pipelined Sync SRAM
[1]
Features Functional Description
• Registered inputs and outputs for pipelined operation The CY7C1364C SRAM integrates 256K x 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
• 256K × 32 common I/O architecture
counter for internal burst operation. All synchronous inputs are
• 3.3V core power supply (V )
DD gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include a
ページ2に含まれる内容の要旨
CY7C1364C Selection Guide 250 MHz 200 MHz 166 MHz Unit Maximum Access Time 2.8 3.0 3.5 ns Maximum Operating Current 250 220 180 mA Maximum CMOS Standby Current 40 40 40 mA Pin Configuration 100-Pin TQFP Pinout (2 Chip Enables) (AJ version) NC 1 80 NC DQ C DQ 2 79 B DQ C 3 78 DQ B V DDQ 4 77 V DDQ V V SSQ 5 76 SSQ DQ C 6 75 DQ B DQ BYTE C BYTE B C DQ 7 74 B DQ C 8 73 DQ B DQ C 9 72 DQ B V SSQ V 10 71 SSQ V DDQ 11 70 V DDQ DQ C 12 69 DQ B DQ DQ C 13 68 B NC 14 67 V SS V CY7C1364C DD NC 15 66 NC
ページ3に含まれる内容の要旨
CY7C1364C Pin Configuration (continued) 100-Pin TQFP Pinout (3 Chip Enables) (A version) NC 1 80 NC DQ C DQ 2 79 B DQ C 3 78 DQ B V DDQ 4 77 V DDQ V V SSQ 5 76 SSQ DQ C 6 75 DQ B DQ BYTE C BYTE B C DQ 7 74 B DQ C 8 73 DQ B DQ C 9 72 DQ B V SSQ V 10 71 SSQ V DDQ 11 70 V DDQ DQ C 12 69 DQ B DQ DQ C 13 68 B NC 14 67 V SS V CY7C1364C DD 15 66 NC NC 16 65 V DD V SS 17 64 ZZ DQ D DQ 18 63 A DQ D 19 62 DQ A V DDQ 20 61 V DDQ V V SSQ 21 60 SSQ DQ D 22 59 DQ A DQ D 23 58 DQ A DQ BYTE D DQ BYTE A D 24 5
ページ4に含まれる内容の要旨
CY7C1364C Pin Definitions Name TQFP I/O Description A , A , A 37, 36, 32, 33, 34, 35, 43, Input- Address Inputs used to select one of the 256K address locations. 0 1 44, 45, 46, 47, 48, 49, 50, Synchronous Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, 81, 82, 99, 100 and CE , CE , and CE are sampled active. A feed the 2-bit counter. 1 2 3 [1:0] BW , BW 93, 94, 95, 96 Input- Byte Write Select Inputs, active LOW. Qualified with BWE to conduct A B BW , BW Synchronous by
ページ5に含まれる内容の要旨
CY7C1364C Pin Definitions (continued) Name TQFP I/O Description V 4, 11, 20, 27, 54, 61, 70, 77 I/O Power Power supply for the I/O circuitry. DDQ Supply V 5, 10, 21, 26, 55, 60, 71, 76 I/O Ground Ground for the I/O circuitry. SSQ MODE 31 Input- Selects Burst Order. When tied to GND selects linear burst sequence. Static When tied to V or left floating selects interleaved burst sequence. DD This is a strap pin and should remain static during device operation. Mode pin has an internal pull-
ページ6に含まれる内容の要旨
CY7C1364C Burst Sequences Interleaved Burst Address Table (MODE = Floating or V ) The CY7C1364C provides a two-bit wraparound counter, fed DD by A , that implements either an interleaved or linear burst [1:0] First Second Third Fourth sequence. The interleaved burst sequence is designed specif- Address Address Address Address ically to support Intel Pentium applications. The linear burst A A A A [1:0] [1:0] [1:0] [1:0] sequence is designed to support processors that follow a 00 01 10 11 lin
ページ7に含まれる内容の要旨
CY7C1364C [3, 4, 5, 6, 7, 8] Truth Table Address Next Cycle Used ZZ CE CE CE ADSP ADSC ADV OE DQ Write 3 2 1 Unselected None L X X H X L X X Tri-State X Unselected None L H X L L X X X Tri-State X Unselected None L X L L L X X X Tri-State X Unselected None L H X L H L X X Tri-State X Unselected None L X L L H L X X Tri-State X Begin Read External L L H L L X X X Tri-State X Begin Read External L L H L H L X X Tri-State Read Continue Read Next L X X X H H L H Tri-State Read Continue Read Next
ページ8に含まれる内容の要旨
CY7C1364C [3, 4] Truth Table for Read/Write Function GW BWE BW BW BW BW D C B A Read H H XXXX Read H L HHHH Write Byte A – DQ H L HHH L A Write Byte B – DQ HL H H L H B Write Bytes B, A H L H H L L Write Byte C – DQ HL HL H H C Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write Bytes C, B, A H L H L L L Write Byte D – DQ H L L HHH D Write Bytes D, A H L L H H L Write Bytes D, B H L L H L H Write Bytes D, B, A H L L H L L Write Bytes D, C H L L L H H Write Bytes D, C, A H L L L H L
ページ9に含まれる内容の要旨
CY7C1364C DC Input Voltage................................... –0.5V to V + 0.5V Maximum Ratings DD Current into Outputs (LOW) .........................................20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage .......................................... >2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-up Current ..................................................
ページ10に含まれる内容の要旨
CY7C1364C [11] Capacitance 100 TQFP Parameter Description Test Conditions Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 5pF IN A V = 3.3V DD C Clock Input Capacitance 5 pF CLK V = 2.5V DDQ C Input/Output Capacitance 5 pF I/O [11] Thermal Resistance Parameter Description Test Conditions 100 TQFP Package Unit Θ Thermal Resistance Test conditions follow standard test 29.41 °C/W JA (Junction to Ambient) methods and procedures for measuring thermal impedance, per EIA/JESD51 Θ Thermal Resist
ページ11に含まれる内容の要旨
CY7C1364C [12,13] Switching Characteristics Over the Operating Range –250 –200 –166 Parameter Description Min. Max. Min. Max. Min. Max. Unit [14] t V (Typical) to the First Access 1 11 ms POWER DD Clock t Clock Cycle Time 4.0 5.0 6.0 ns CYC t Clock HIGH 1.8 2.0 2.4 ns CH t Clock LOW 1.8 2.0 2.4 ns CL Output Times t Data Output Valid after CLK Rise 2.8 3.0 3.5 ns CO t Data Output Hold after CLK Rise 1.25 1.25 1.25 ns DOH [15, 16, 17] t Clock to Low-Z 1.25 1.25 1.25 ns CLZ [15, 16, 17] t Clock
ページ12に含まれる内容の要旨
CY7C1364C Switching Waveforms [18] Read Cycle Timing t CYC CLK t t CL CH t t ADS ADH ADSP t t ADH ADS ADSC t t AS AH ADDRESS A1 A2 A3 Burst continued with t t WES WEH new base address GW, BWE, BW[A:D] Deselect t t CES CEH cycle CE t t ADVS ADVH ADV ADV suspends burst. OE t t OEV CO t t OEHZ t t CHZ OELZ DOH t CLZ Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Data Out (Q) Q(A1) High-Z t CO Burst wraps around Note: to its initial state 18. On this diagram, when CE is LOW, CE is LOW, CE
ページ13に含まれる内容の要旨
CY7C1364C Switching Waveforms (continued) [18,19] Write Cycle Timing t CYC CLK t t CL CH t t ADH ADS ADSP ADSC extends burst t t ADS ADH t t ADS ADH ADSC t t AS AH ADDRESS A1 A2 A3 Byte write signals are ignored for first cycle when t t ADSP initiates burst WEH WES BWE, BW[A :D] t t WES WEH GW t t CEH CES CE t t ADVS ADVH ADV ADV suspends burst OE t t DS DH Data In (D) D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) High-Z t OEHZ Data Out (Q) BURST READ Single W
ページ14に含まれる内容の要旨
CY7C1364C Switching Waveforms (continued) [18,20, 21] Read/Write Cycle Timing t CYC CLK t t CL CH t t ADS ADH ADSP ADSC t t AS AH ADDRESS A1 A2 A3 A4 A5 A6 t t WEH WES BWE, BW[A:D] t t CES CEH CE ADV OE t t t CO DS DH t OELZ Data In (D) D(A3) D(A5) D(A6) High-Z t t OEHZ CLZ Data Out (Q) Q(A1) Q(A2) Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) High-Z Back-to-Back READs Single WRITE BURST READ Back-to-Back WRITEs DON’T CARE UNDEFINED Notes: 20. The data bus (Q) remains in High-Z following a Write cycle unle
ページ15に含まれる内容の要旨
CY7C1364C Switching Waveforms (continued) [22, 23] ZZ Mode Timing CLK t t ZZ ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI ALL INPUTS DESELECT or READ Only (except ZZ) Outputs (Q) High-Z DON’T CARE Notes: 22. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 23. DQs are in High-Z when exiting ZZ sleep mode. Document #: 38-05689 Rev. *E Page 15 of 18 [+] Feedback
ページ16に含まれる内容の要旨
CY7C1364C Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed Package Operating (MHz) Ordering Code Diagram Part and Package Type Range 166 CY7C1364C-166AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial (3 Chip Enable) CY7C1364C-166AJXC 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free (2 Chip Enable) CY7C1364C-16
ページ17に含まれる内容の要旨
CY7C1364C Package Diagram 100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050) 16.00±0.20 1.40±0.05 14.00±0.10 100 81 1 80 0.30±0.08 0.65 12°±1° SEE DETAIL A TYP. (8X) 30 51 31 50 0.20 MAX. 1.60 MAX. R 0.08 MIN. 0° MIN. 0.20 MAX. SEATING PLANE STAND-OFF 0.05 MIN. NOTE: 0.25 0.15 MAX. 1. JEDEC STD REF MS-026 GAUGE PLANE 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE R 0.08 MIN. 0°-7° BODY LENGTH DIMENSIONS ARE M
ページ18に含まれる内容の要旨
CY7C1364C Document History Page Document Title: CY7C1364C 9-Mbit (256K x 32) Pipelined Sync SRAM Document Number: 38-05689 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 286269 See ECN PCI New data sheet *A 320834 See ECN PCI Changed 225 MHz into 250 MHz Changed Θ and Θ for TQFP from 25 and 9 °C/W to 29.41 and 6.13 °C/W JA JC respectively Modified V V test conditions OL, OH Added Industrial Operating Range Changed Snooze to Sleep in the ZZ Mode Electrical Characteristic
