ページ1に含まれる内容の要旨
CY7C09079V/89V/99V
CY7C09179V/89V/99V
CY7C09079V/89V/99V
CY7C09179V/89V/99V
3.3V 32K/64K/128K x 8/9
Synchronous Dual-Port Static RAM
■ High speed clock to data access 6.5[1]/7.5[1]/9/12 ns (max.)
Features
■ 3.3V low operating power
■ True Dual-Ported memory cells which enable simultaneous
access of the same memory location
■ Active= 115 mA (typical)
■ 6 Flow-Through and Pipelined devices
■ Standby= 10 μA (typical)
■ 32K x 8/9 organizations (CY7C09079V/179V)
■ Fully synchronous interface for
ページ2に含まれる内容の要旨
CY7C09079V/89V/99V CY7C09179V/89V/99V A HIGH on CE or LOW on CE for one clock cycle powers down Functional Description 0 1 the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables enables easier banking of multiple The CY7C09079V/89V/99V and CY7C09179V/89V/99V are chips for depth expansion configurations. In the pipelined mode, high speed synchronous CMOS 32K, 64K, and 128K x 8/9 one cycle is required with CE LOW and CE HIGH to reactivate dual-port static
ページ3に含まれる内容の要旨
CY7C09079V/89V/99V CY7C09179V/89V/99V Pin Configurations (continued Figure 2. 100-Pin TQFP (Top View0 - CY7C09199V (128K x 9), CY7C09189V (64K x 9),CY7C09179V (32K x 9) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC 1 75 NC NC 2 74 NC A7L 3 73 A7R A8L 4 72 A8R A9L 5 71 A9R 70 A10R A10L 6 A11L 7 69 A11R A12L 8 68 A12R A13L 9 67 A13R A14L 10 66 A14R [8] [8] A15L 11 65 A15R [9] [9] A16L 12 64 A16R VCC 13 63 GND 62 NC NC 14 NC 15 61 NC NC 16 60 NC NC 17 59 NC C
ページ4に含まれる内容の要旨
CY7C09079V/89V/99V CY7C09179V/89V/99V Selection Guide CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09079V/89V/99V CY7C09079V/89V/99V Description CY7C09179V/89V/99V CY7C09179V/89V/99V [1] [1] CY7C09179V/89V/99V-6 CY7C09179V/89V/99V-7 -9 -12 f (MHz) 100 83 67 50 MAX2 (Pipelined) Max. Access Time 6.5 7.5 9 12 (ns) (Clock to Data, Pipelined) Typical Operating 175 155 135 115 Current I (mA) CC Typical Standby 25 25 20 20 Current for I SB1 (mA) (Both Ports TTL Level) Typical Standby 10 μA 10 μA10 μA
ページ5に含まれる内容の要旨
CY7C09079V/89V/99V CY7C09179V/89V/99V Static Discharge Voltage............................................ >2001V Maximum Ratings Latch-Up Current..................................................... >200 mA Exceeding maximum ratings may impair the useful life of the [10] device. These user guidelines are not tested. Operating Range Storage Temperature................................. –65°C to +150°C Ambient Ambient Temperature with Power Applied..–55°C to +125°C Range Temperature V CC Supply
ページ6に含まれる内容の要旨
CY7C09079V/89V/99V CY7C09179V/89V/99V Figure 3. AC Test Loads 3.3V 3.3V R = 250Ω R1 = 590Ω TH OUTPUT OUTPUT R1 = 590Ω OUTPUT C= 30 pF C= 30 pF R2 = 435Ω C= 5pF R2 = 435Ω V =1.4V TH (a) Normal Load (Load 1) (c) Three-State Delay(Load 2) (b) Thévenin Equivalent (Load 1) (Used for t , t , & t CKLZ OLZ OHZ including scope and jig) [13] Figure 4. AC Test Loads (Applicable to -6 and -7 only) ALL INPUTPULSES Z = 50Ω R = 50Ω 0 OUTPUT 3.0V 90% 90% C 10% 10% GND 3 ns V =1.4V 3ns ≤ ≤ TH (a) Load 1 (-6
ページ7に含まれる内容の要旨
CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Characteristics Over the Operating Range CY7C09079V/89V/99V CY7C09179V/89V/99V Parameter Description [1] [1] -6 -7 -9 -12 Min Max Min Max Min Max Min Max Unit f f Flow-Through 53 45 40 33 MHz MAX1 Max f f Pipelined 100 83 67 50 MHz MAX2 Max t Clock Cycle Time - Flow-Through 19 22 25 30 ns CYC1 t Clock Cycle Time - Pipelined 10 12 15 20 ns CYC2 t Clock HIGH Time - Flow-Through 6.5 7.5 12 12 ns CH1 t Clock LOW Time - Flow-Through 6.5 7.5 12 12 ns C
ページ8に含まれる内容の要旨
CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) [16, 17, 18, 19] Figure 6. Read Cycle for Flow-Through Output (FT/PIPE = V ) IL t CYC1 t t CH1 CL1 CLK CE 0 t t t t SC HC SC HC CE 1 R/W t t SW HW t t SA HA A A A A n n+1 n+2 n+3 ADDRESS t CKHZ t t DC CD1 DATA OUT Q Q Q n n+1 n+2 t t DC CKLZ t t OHZ OLZ OE t OE Notes 16. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 17. ADS = V , CNTEN and CNTRST = V . IL IH 18. The output is di
ページ9に含まれる内容の要旨
CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) [16, 17, 18, 19] Figure 7. Read Cycle for Pipelined Operation (FT/PIPE = V ) IH t CYC2 t t CH2 CL2 CLK CE 0 t t t t SC HC SC HC CE 1 R/W t t SW HW t t SA HA ADDRESS A A A A n n+1 n+2 n+3 t 1 Latency t DC CD2 DATA OUT Q Q Q n n+1 n+2 t OHZ t t CKLZ OLZ OE t OE [20, 21] Figure 8. Bank Select Pipelined Read - t CYC2 t t CH2 CL2 CLK L t t HA SA ADDRESS A A A A A (B1) A 3 4 5 0 1 2 t t HC SC CE 0(B1) t t t t t t t CD2 HC CD2 CD
ページ10に含まれる内容の要旨
CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) [22, 23, 24, 25] Figure 9. Left Port Write to Flow-Through Right Port Read CLK L t t HW SW R/W L t t HA SA NO ADDRESS MATCH L MATCH t t HD SD VALID DATA INL t CCS CLK R t CD1 t t SW HW R/W R t t SA HA NO ADDRESS MATCH R MATCH t t CWDD CD1 DATA VALID VALID OUTR t DC t DC Notes 20. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet.
ページ11に含まれる内容の要旨
CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) [19, 26, 27, 28] Figure 10. Pipelined Read-to-Write-to-Read (OE = V ) IL t CYC2 t t CH2 CL2 CLK CE 0 t t SC HC CE 1 t t SW HW R/W t t SW HW A A A A A A n n+1 n+2 n+2 n+3 n+4 ADDRESS t t SD HD t t SA HA DATA D IN n+2 t t t t CD2 CD2 CKHZ CKLZ Q Q n n+3 DATA OUT READ NO OPERATION WRITE READ Document #: 38-06043 Rev. *C Page 11 of 21 [+] Feedback
ページ12に含まれる内容の要旨
CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) [19, 26, 27, 28] Figure 11. Pipelined Read-to-Write-to-Read (OE Controlled) t CYC2 t t CH2 CL2 CLK CE 0 t t SC HC CE 1 t t SW HW R/W t t SW HW A A A A A A n n+1 n+2 n+3 n+4 n+5 ADDRESS t t t t SA HA SD HD DATA D D IN n+2 n+3 t t t CD2 CKLZ CD2 DATA OUT Q Q n n+4 t OHZ OE READ WRITE READ Notes 26. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. 27. CE and ADS = V ; CE , CNTEN,
ページ13に含まれる内容の要旨
CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) [17, 19, 26, 27, 28] Figure 12. Flow-Through Read-to-Write-to-Read (OE = V ) IL t CYC1 t t CH1 CL1 CLK CE 0 t t SC HC CE 1 t t SW HW R/W t t SW HW A A A A A A n n+1 n+2 n+2 n+3 n+4 ADDRESS t t SD HD t t SA HA D n+2 DATA IN t t t t CD1 CD1 CD1 CD1 DATA Q Q Q OUT n n+1 n+3 t t t t DC CKHZ CKLZ DC NO READ WRITE READ OPERATION [17, 20, 26, 27, 28] Figure 13. Flow-Through Read-to-Write-to-Read (OE Controlled) t CYC1 t t CH1 CL1
ページ14に含まれる内容の要旨
CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) [29] Figure 14. Pipelined Read with Address Counter Advance t CYC2 t t CH2 CL2 CLK t t SA HA ADDRESS A n t t SAD HAD ADS t t SAD HAD CNTEN t t SCN HCN t t SCN HCN t CD2 DATA OUT Q Q Q Q Q Q x-1 x n n+1 n+2 n+3 READ t DC COUNTER HOLD READ WITH COUNTER READ WITH COUNTER EXTERNAL ADDRESS [29] Figure 15. Flow-Through Read with Address Counter Advance t CYC1 t t CH1 CL1 CLK t t SA HA A n ADDRESS t t SAD HAD ADS t t SAD HAD CNTE
ページ15に含まれる内容の要旨
CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) [30, 31] Figure 16. Write with Address Counter Advance (Flow-Through or Pipelined Outputs) t CYC2 t t CH2 CL2 CLK t t SA HA A ADDRESS n INTERNAL A A A A A n n+1 n+2 n+3 n+4 ADDRESS t t SAD HAD ADS CNTEN t t SCN HCN D D D D D D DATA n n+1 n+1 n+2 n+3 n+4 IN t t SD HD WRITE EXTERNAL WRITE WITH WRITE COUNTER WRITE WITH COUNTER ADDRESS COUNTER HOLD Notes 30. CE and R/W = V ; CE and CNTRST = V . 0 IL 1 IH 31. The “Internal Addre
ページ16に含まれる内容の要旨
CY7C09079V/89V/99V CY7C09179V/89V/99V Switching Waveforms (continued) [19, 26, 32, 33] Figure 17. Counter Reset (Pipelined Outputs) t CYC2 t t CH2 CL2 CLK t t SA HA A A ADDRESS n n+1 INTERNAL A 01A A X n n+1 ADDRESS t t SW HW R/W t t SAD HAD ADS t t SCN HCN CNTEN t t SRST HRST CNTRST t t SD HD DATA D IN 0 DATA Q Q Q OUT 0 1 n COUNTER WRITE READ READ READ RESET ADDRESS 0 ADDRESS 0 ADDRESS 1 ADDRESS n Notes 32. CE = V ; CE = V . 0 IL 1 IH 33. No dead cycle exists during counter reset. A READ or
ページ17に含まれる内容の要旨
CY7C09079V/89V/99V CY7C09179V/89V/99V [34, 35, 36] Table 1. Read/Write and Enable Operation Inputs Outputs OE CLK CE CE R/W I/O –I/O Operation 0 1 0 9 [37] X H X X High-Z Deselected [37] X X L X High-Z Deselected X L H L D Write IN [37] L L H H D Read OUT H X L H X High-Z Outputs Disabled [34, 38, 39, 40] Table 2. Address Counter Control Operation Previous Address CLK ADS CNTEN CNTRST I/O Mode Operation Address X X X X L D Reset Counter Reset to Address 0 out(0) A X L X H D Load Address Load
ページ18に含まれる内容の要旨
CY7C09079V/89V/99V CY7C09179V/89V/99V Ordering Information 32K x8 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range [1] 6.5 CY7C09079V-6AC A100 100-Pin Thin Quad Flat Pack Commercial [1] 7.5 CY7C09079V-7AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09079V-7AI A100 100-Pin Thin Quad Flat Pack Industrial 9 CY7C09079V-9AC A100 100-Pin Thin Quad Flat Pack Commercial 12 CY7C09079V-12AC A100 100-Pin Thin Quad Flat Pack Commercial 64K x8 3.3V Sync
ページ19に含まれる内容の要旨
CY7C09079V/89V/99V CY7C09179V/89V/99V 64K x9 3.3V Synchronous Dual-Port SRAM Speed (ns) Ordering Code Package Name Package Type Operating Range [1] 6.5 CY7C09189V-6AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09189V-6AXC A100 100-Pin Pb-Free Thin Quad Flat Pack Commercial [1] 7.5 CY7C09189V-7AC A100 100-Pin Thin Quad Flat Pack Commercial 9 CY7C09189V-9AC A100 100-Pin Thin Quad Flat Pack Commercial 12 CY7C09189V-12AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C09189V-12AXC A100 100-Pi
ページ20に含まれる内容の要旨
CY7C09079V/89V/99V CY7C09179V/89V/99V Package Diagram Figure 18. 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 (51-85048) 51-85048-*B Document #: 38-06043 Rev. *C Page 20 of 21 [+] Feedback
