ページ1に含まれる内容の要旨
CY7C1241V18, CY7C1256V18
CY7C1243V18, CY7C1245V18
36-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.0 Cycle Read Latency)
Features Configurations
■ Separate independent read and write data ports With Read Cycle Latency of 2.0 cycles:
❐ Supports concurrent transactions
CY7C1241V18 – 4M x 8
CY7C1256V18 – 4M x 9
■ 300 MHz to 375 MHz clock for high bandwidth
CY7C1243V18 – 2M x 18
■ 4-Word Burst for reducing address bus frequency
CY7C1245V18 – 1M x 36
■ Double Data Rate (DDR) interfaces on both re
ページ2に含まれる内容の要旨
1M x 8 Array 1M x 9 Array 1M x 8 Array 1M x 9 Array 1M x 8 Array 1M x 9 Array 1M x 8 Array 1M x 9 Array CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Logic Block Diagram (CY7C1241V18) D [7:0] 8 Write Write Write Write Address A Reg Reg Reg Reg (19:0) Address Register 20 Register A (19:0) 20 RPS K Control CLK K Logic Gen. DOFF Read Data Reg. CQ CQ 32 16 V REF Reg. Reg. WPS Control Q [7:0] 16 Logic NWS [1:0] Reg. 8 8 QVLD Logic Block Diagram (CY7C1256V18) D [8:0] 9 Write Write Write Write Addr
ページ3に含まれる内容の要旨
512K x 18 Array 256K x 36 Array 512K x 18 Array 256K x 36 Array 512K x 18 Array 256K x 36 Array 512K x 18 Array 256K x 36 Array CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Logic Block Diagram (CY7C1243V18) D [17:0] 18 Write Write Write Write Address A Reg Reg Reg Reg (18:0) Address Register 19 Register A (18:0) 19 K RPS Control CLK K Logic Gen. DOFF Read Data Reg. CQ 72 CQ 36 V REF Reg. Reg. WPS Control Q [17:0] 36 Logic BWS [1:0] Reg. 18 18 QVLD Logic Block Diagram (CY7C1245V18) D [35:0]
ページ4に含まれる内容の要旨
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Pin Configurations 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1241V18 (4M x 8) 1 23 6 910 11 5 7 8 4 A NC/72M A NC/ NC/14 144M 4M AA CQ CQ WPS NWS K RPS 1 B NC NC NC A NC/288M K NWS A NC NC Q3 0 NC NC NC V ANCA V NC NC D3 C SS SS NC D4 NC V V V V V NC NC NC D SS SS SS SS SS NC NC Q4 V V V V V NC D2 Q2 E DDQ SS SS SS DDQ NC V V V NC F NC NC V V NC NC DDQ DD SS DD DDQ NC D5 Q5 V V V V V NC NC NC G DDQ DD SS DD DDQ V V V V V V V V V ZQ H DOFF REF
ページ5に含まれる内容の要旨
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1243V18 (2M x 18) 1 23 4 56 7 8 910 11 A NC/144M A NC/288M A NC/72M CQ CQ WPS BWS K RPS 1 NC Q9 D9 A NC K A NC NC Q8 B BWS 0 NC ANC A NC Q7 D8 C NC D10 V V SS SS NC D11 Q10 V V V V V NC NC D7 D SS SS SS SS SS NC NC Q11 V V V V V NC D6 Q6 E DDQ SS SS SS DDQ F NC Q12 D12 V V V V V NC NC Q5 DDQ DD SS DD DDQ G NC D13 Q13 V V V V V NC NC D5 DDQ DD SS DD DDQ V V V V V V V V V ZQ
ページ6に含まれる内容の要旨
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Pin Definitions Pin Name IO Pin Description D Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations. Input- [x:0] Synchronous CY7C1241V18 − D [7:0] CY7C1256V18 − D [8:0] CY7C1243V18 − D [17:0] CY7C1245V18 − D [35:0] WPS Input- Write Port Select, Active LOW. Sampled on the rising edge of the K clock. When asserted Synchronous active, a Write operation is initiated. Deasserting deselects the write port. De
ページ7に含まれる内容の要旨
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Pin Definitions (continued) Pin Name IO Pin Description CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock (K) of the QDR-II+. The timing for the echo clocks is shown in “Switching Character- istics” on page 23. CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock (K) of the QDR-II+. The timing for the echo clocks is shown
ページ8に含まれる内容の要旨
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Write Operations Functional Overview Write operations are initiated by asserting WPS active at the The CY7C1241V18, CY7C1256V18, CY7C1243V18, and rising edge of the Positive Input Clock (K). On the following K CY7C1245V18 are synchronous pipelined Burst SRAMs clock rise, the data presented to D is latched and stored into [17:0] equipped with a read and a write port. The read port is dedicated the lower 18-bit Write Data register, provided BWS are
ページ9に含まれる内容の要旨
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Depth Expansion Valid Data Indicator (QVLD) The CY7C1243V18 has a Port Select input for each port. This QVLD is provided on the QDR-II+ to simplify data capture on high enables easy depth expansion. Both Port Selects are sampled speed systems. The QVLD is generated by the QDR-II+ device on the rising edge of the Positive Input Clock only (K). Each port along with data output. This signal is also edge-aligned with the select input can deselect the
ページ10に含まれる内容の要旨
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Application Example Figure 1 shows the use of 4 QDR-II+ SRAMs in an application. Figure 1. Application Example RQ = 250ohms RQ = 250ohms ZQ ZQ Vt SRAM #1 CQ/CQ SRAM #4 CQ/CQ D Q D Q R A RPS WPS BWS K K A K K RPS WPS BWS DATA IN R DATA OUT Vt Address Vt R RPS BUS MASTER WPS (CPU or ASIC) BWS CLKIN/CLKIN Source K Source K R = 50ohms, Vt = V /2 DDQ Truth Table [2, 3, 4, 5, 6, 7] The truth table for the CY7C1241V18, CY7C1256V18, CY7C1243V18,
ページ11に含まれる内容の要旨
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Write Cycle Descriptions [2, 10] The write cycle description table for CY7C1241V18 and CY7C1243V18 follows. BWS / BWS / 0 1 K Comments K NWS NWS 0 1 L L L–H – During the data portion of a write sequence: CY7C1241V18 − both nibbles (D ) are written into the device. [7:0] CY7C1243V18 − both bytes (D ) are written into the device. [17:0] L L – L-H During the data portion of a write sequence: CY7C1241V18 − both nibbles (D ) are written into the de
ページ12に含まれる内容の要旨
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Write Cycle Descriptions [2, 10] The write cycle description table for CY7C1245V18 follows. BWS BWS BWS BWS K K Comments 0 1 2 3 LLLL L–H – During the data portion of a write sequence, all four bytes (D ) are written [35:0] into the device. LLLL – L–H During the data portion of a write sequence, all four bytes (D ) are written [35:0] into the device. L H H H L–H – During the data portion of a write sequence, only the lower byte (D ) is [8:0]
ページ13に含まれる内容の要旨
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Instruction Register IEEE 1149.1 Serial Boundary Scan (JTAG) Three-bit instructions can be serially loaded into the instruction These SRAMs incorporate a serial boundary scan test access register. This register is loaded when it is placed between the TDI port (TAP) in the FBGA package. This part is fully compliant with and TDO pins as shown in “TAP Controller Block Diagram” on IEEE Standard #1149.1-2001. The TAP operates using JEDEC page 16. Upon
ページ14に含まれる内容の要旨
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 IDCODE PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection The IDCODE instruction loads a vendor-specific, 32-bit code into of another boundary scan test operation. the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the The shifting of data for the SAMPLE and PRELOAD phases can device when the TAP co
ページ15に含まれる内容の要旨
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 TAP Controller State Diagram [11] The state diagram for the CY7C1241V18, CY7C1256V18, CY7C1243V18, and CY7C1245V18 follows. TEST-LOGIC 1 RESET 0 1 1 1 TEST-LOGIC/ SELECT SELECT 0 IDLE DR-SCAN IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 0 1 1 1 1 EXIT1-DR EXIT1-IR 0 0 0 0 PAUSE-DR PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR UPDATE-IR 1 1 0 0 Note 11. The 0/1 next to each state represents the value at TMS at the rising edge o
ページ16に含まれる内容の要旨
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 TAP Controller Block Diagram 0 Bypass Register Selection TDI Selection 2 1 0 TDO Circuitry Circuitry Instruction Register 29 31 30 . . 2 1 0 Identification Register . 108 . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics [12, 13, 14] Over the Operating Range Parameter Description Test Conditions Min Max Unit V Output HIGH Voltage I = −2.0 mA 1.4 V OH1 OH V Output HIGH Voltage I = −100 μA1.6 V OH2 OH V Out
ページ17に含まれる内容の要旨
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 TAP AC Switching Characteristics [15, 16] Over the Operating Range Parameter Description Min Max Unit t TCK Clock Cycle Time 50 ns TCYC t TCK Clock Frequency 20 MHz TF t TCK Clock HIGH 20 ns TH t TCK Clock LOW 20 ns TL Setup Times t TMS Setup to TCK Clock Rise 5 ns TMSS t TDI Setup to TCK Clock Rise 5 ns TDIS t Capture Setup to TCK Rise 5 ns CS Hold Times t TMS Hold after TCK Clock Rise 5 ns TMSH t TDI Hold after Clock Rise 5 ns TDIH t Capture
ページ18に含まれる内容の要旨
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Identification Register Definitions Value Instruction Description Field CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18 Revision 000 000 000 000 Version number. Number (31:29) Cypress Device 11010010101000111 11010010101001111 11010010101010111 11010010101100111 Defines the type ID (28:12) of SRAM. Cypress JEDEC 00000110100 00000110100 00000110100 00000110100 Enables unique ID (11:1) identification of SRAM vendor. ID Register 1111 Indicates
ページ19に含まれる内容の要旨
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P29 9G 57 5B85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N32 9F 60 5C88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43 11C
ページ20に含まれる内容の要旨
CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 Power Up Sequence in QDR-II+ SRAM DLL Constraints QDR-II+ SRAMs must be powered up and initialized in a ■ DLL uses K clock as its synchronizing input. The input must predefined manner to prevent undefined operations. During have low phase jitter, which is specified as t . KC Var power up, when the DOFF is tied HIGH, the DLL is locked after ■ The DLL functions at frequencies down to 120 MHz. 2048 cycles of stable clock. ■ If the input clock is uns
