ページ1に含まれる内容の要旨
CY7C0430BV
CY7C0430CV
10 Gb/s 3.3V QuadPort™ DSE Family
• Dual Chip Enables on all ports for easy depth expansion
Features
• Separate upper-byte and lower-byte controls on all
• QuadPort™ datapath switching element (DSE) family
ports
allows four independent ports of access for data path
• Simple array partitioning
management and switching
— Internal mask register controls counter wrap-around
• High-bandwidth data throughput up to 10 Gb/s
[1]
— Counter-Interrupt flags to indicate wrap-aroun
ページ2に含まれる内容の要旨
CY7C0430BV CY7C0430CV PORT 1 PORT 2 PORT 4 PORT 3 DATA PATH AGGREGATOR Processor 1 QuadPort Pre-processed DATA Path Processed DATA Path DSE Family Processor 2 DATA PATH MANAGER FOR PARALLEL PACKET PROCESSING Queue #1 PORT 1 PORT 3 Queue #2 PORT 2 PORT 4 DATA CLASSIFICATION ENGINE address register. After externally loading the counter with the Functional Description initial address the counter will self-increment the address inter- The Quadport Datapath Switching Element (DSE) family offers
ページ3に含まれる内容の要旨
CY7C0430BV CY7C0430CV counter is loaded with an external address when the port’s mask register operations are described in more details in the Counter Load pin (CNTLD) is asserted LOW. When the port’s following sections. Counter Increment pin (CNTINC) is asserted, the address The counter or mask register values can be read back on the counter will increment on each subsequent LOW-to- HIGH bidirectional address lines by activating MKRD or CNTRD, transition of that port’s clock signal. This will
ページ4に含まれる内容の要旨
Port 4 Port 2 CY7C0430BV CY7C0430CV Port 1 Operation-Control Logic Block Diagram (Address Readback is independent of CEs) R/W P1 W UB P1 CE 0P1 CE 1P1 LB P1 OE P1 9 I/O –I/O 9P1 17P1 Port-1 I/O Control 9 I/O –I/O 0P1 8P1 Addr. Read Port 1 Readback Register MRST 16 A –A 0P1 15P1 Port 1 Mask Register CNTRD P1 Port 1 Priority 64K × 18 MKRD P1 Address QuadPort Decision MKLD Port 1 P1 DSE Array Decode Logic Counter/ CNTINC P1 Address Register CNTLD P1 CNTRST P1 LB P1 CLK UB P1 P1 Port 1 R/W P1 MRST
ページ5に含まれる内容の要旨
CY7C0430BV CY7C0430CV Pin Configuration 272-ball Grid Array (BGA) Top View 123456789 10 11 12 13 14 15 16 17 18 19 20 LB I/O17 I/O15 I/O13 I/O11 I/O9 I/O16 I/O14 I/O12 I/O10 I/O10 I/O12 I/O14 I/O16 I/O9 I/O11 I/O13 I/O15 I/O17 LB A P1 P2 P2 P2 P2 P2 P1 P1 P1 P1 P4 P4 P4 P4 P3 P3 P3 P3 P3 P4 VDD1 UB I/O16 I/O14 I/O12 I/O10 I/O17 I/O13 I/O11 TMS TDI I/O11 I/O13 I/O17 I/O10 I/O12 I/O14 I/O16 UB VDD1 B P1 P2 P2 P2 P2 P1 P1 P1 P4 P4 P4 P3 P3 P3 P3 P4 A14 A15 CE1 CE0 R/W I/O15 VSS2 VSS2 I/O9 TCK TDO
ページ6に含まれる内容の要旨
CY7C0430BV CY7C0430CV Selection Guide CY7C0430CV CY7C0430CV –133 –100 Unit [1] f 133 100 MHz MAX2 Max Access Time (Clock to Data) 4.2 5.0 ns Max Operating Current I 750 600 mA CC Max Standby Current for I (All ports TTL Level) 200 150 mA SB1 Max Standby Current for I (All ports CMOS Level) 15 15 mA SB3 Pin Definitions Port 1 Port 2 Port 3 Port 4 Description A –A A –A A –A A –A Address Input/Output. 0P1 15P1 0P2 15P2 0P3 15P3 0P4 15P4 I/O –I/O I/O –I/O I/O –I/O I/O –I/O Data Bus Input/Outp
ページ7に含まれる内容の要旨
CY7C0430BV CY7C0430CV Pin Definitions (continued) Port 1 Port 2 Port 3 Port 4 Description CNTRD CNTRD CNTRD CNTRD Counter Readback Input. When asserted LOW, the P1 P2 P3 P4 internal address value of the counter will be read back on the address lines. During CNTRD operation, both CNTLD and CNTINC must be HIGH. Counter readback operation has higher priority over mask register readback operation. Counter readback operation is independent of port chip enables. If address readback operation
ページ8に含まれる内容の要旨
CY7C0430BV CY7C0430CV Maximum Ratings (Above which the useful life may be impaired. For user guide- Output Current into Outputs (LOW)............................. 20 mA lines, not tested.) Static Discharge Voltage........................................... > 2200V Storage Temperature ................................ –65°C to + 150°C Latch-up Current..................................................... > 200 mA Ambient Temperature with Operating Range Power Applied.............................
ページ9に含まれる内容の要旨
CY7C0430BV CY7C0430CV AC Test Load Z = 50Ω R = 50Ω 0 Z = 50Ω R = 50Ω 0 OUTPUT OUTPUT [5] C 5 pF V =1.5V TH V =1.5V TH (a) Normal Load Z = 50Ω R = 50Ω 0 OUTPUT 5 pF V =3.3V TH 1.5V (b) Three-State Delay 50Ω TDO Z =50Ω 0 C = 10 pF 3.0V 90% 90% 10% 10% GND GND t t F R (c) TAP Load All Input Pulses Note: 5. Test conditions: C = 10 pF. Document #: 38-06027 Rev. *B Page 9 of 37 [+] Feedback
ページ10に含まれる内容の要旨
CY7C0430BV CY7C0430CV [6] Switching Characteristics Over the Industrial Operating Range CY7C0430BV and CY7C0430CV –133 –100 Parameter Description Min. Max. Min. Max. Unit [7] f Maximum Frequency 133 100 MHz MAX2 [7] t Clock Cycle Time 7.5 10 ns CYC2 t Clock HIGH Time 3 4 ns CH2 t Clock LOW Time 3 4 ns CL2 t Clock Rise Time 2 3 ns R t Clock Fall Time 2 3 ns F t Address Set-up Time 2.3 3 ns SA t Address Hold Time 0.7 0.7 ns HA t Chip Enable Set-up Time 2.3 3 ns SC t Chip Enable Hold Time 0.7
ページ11に含まれる内容の要旨
CY7C0430BV CY7C0430CV [6] Switching Characteristics Over the Industrial Operating Range (continued) CY7C0430BV and CY7C0430CV –133 –100 Parameter Description Min. Max. Min. Max. Unit [9] t Clock HIGH to Output Low-Z 1 1 ns CKLZ t Clock to INT Set Time 1 7.5 1 10 ns SINT t Clock to INT Reset Time 1 7.5 1 10 ns RINT t Clock to CNTINT Set Time 1 7.5 1 10 ns SCINT t Clock to CNTINT Reset Time 1 7.5 1 10 ns RCINT Master Reset Timing t Master Reset Pulse Width 7.5 10 ns RS t Master Reset Recovery T
ページ12に含まれる内容の要旨
CY7C0430BV CY7C0430CV t t TH TL Test Clock TCK t TCYC t TMSH t TMSS Test Mode Select TMS t t TDIS TDIH Test Data-In TDI Test Data-Out TDO t TDOX t TDOV Switching Waveforms [10] Master Reset t CYC2 t t CH2 CL2 CLK t RS MRST t ALL RSF ADDRESS/ DATA LINES t t S RSR ALL OTHER INACTIVE ACTIVE INPUTS [11] TMS CNTINT INT TDO Notes: 10. t is the set-up time required for all input control signals. S 11. To Reset the test port without resetting the device, TMS must be held low for five clock cycl
ページ13に含まれる内容の要旨
CY7C0430BV CY7C0430CV Switching Waveforms (continued) [12, 13, 14, 15, 16] Read Cycle t CYC2 t t CH2 CL2 CLK CE t t t t SC HC SC HC LB t SB t HB UB R/W t t SW HW t t SA HA ADDRESS A A A A n n+1 n+2 n+3 t 1 Latency t DC CD2 DATA OUT Q Q Q n n+1 n+2 t OHZ t t CKLZ OLZ OE t OE Notes: 12. OE is asynchronously controlled; all other inputs (excluding MRST) are synchronous to the rising clock edge. 13. CNTLD = V , MKLD = V , CNTINC = x, and MRST = CNTRST = V . IL IH IH 14. The output is disabled (h
ページ14に含まれる内容の要旨
CY7C0430BV CY7C0430CV Switching Waveforms (continued) [17, 18] Bank Select Read t CYC2 t t CH2 CL2 CLK t t HA SA A ADDRESS A A A A A 3 4 (B1) 0 1 5 2 t t SC HC CE (B1) t t t t t t t CD2 HC CD2 CKHZ CD2 CKHZ SC Q Q Q 3 DATA 0 1 OUT(B1) t t HA SA t t t DC DC CKLZ A A ADDRESS A A A A 3 4 (B2) 0 1 5 2 t t HC SC CE (B2) t t t t CD2 CKHZ CD2 t SC HC DATA OUT(B2) Q Q 4 2 t t CKLZ CKLZ [19, 20, 21, 22] Read-to-Write-to-Read (OE = V ) IL t CYC2 t t CH2 CL2 CLK CE t t SC HC t t SW HW R/W t t SW HW A A
ページ15に含まれる内容の要旨
CY7C0430BV CY7C0430CV Switching Waveforms (continued) [19, 20, 21, 22] Read-to-Write-to-Read (OE Controlled) t CYC2 t t CH2 CL2 CLK CE t t SC HC t t HW SW R/W t t SW HW A A A A A A n n+1 n+2 n+3 n+4 n+5 ADDRESS t t t t SA HA SD HD DATA D D IN n+2 n+3 t t CD2 CD2 DATA OUT Q Q n n+4 t t OHZ CKLZ OE Read Write Read [23, 24] Read with Address Counter Advance t CYC2 t t CH2 CL2 CLK t t SA HA ADDRESS A n t t SCLD HCLD CNTLD t SCINC t HCINC CNTINC t CD2 DATA OUT Q Q Q Q Q Q x–1 x n n+1 n+2 n+3 Rea
ページ16に含まれる内容の要旨
CY7C0430BV CY7C0430CV Switching Waveforms (continued) [24, 25] Write with Address Counter Advance t CYC2 t t CH2 CL2 CLK t t SA HA A ADDRESS n INTERNAL A A A A A n n+1 n+2 n+3 n+4 ADDRESS t t SCLD HCLD CNTLD CNTINC t t SCINC HCINC D D D D D D DATA n n+1 n+1 n+2 n+3 n+4 IN t t SD HD Write External Write with Write Counter Write with Counter Address Counter Hold Note: = LB = UB = R/W = V ; CE = CNTRST = MRST = MKLD = MKRD = CNTRD = V 25. CE 0 IL 1 IH. Document #: 38-06027 Rev. *B Page 16 of
ページ17に含まれる内容の要旨
CY7C0430BV CY7C0430CV Switching Waveforms (continued) [21, 26, 27] Counter Reset t CYC2 t t CH2 CL2 CLK t t SA HA ADDRESS A A n n+1 INTERNAL A A A A A X 0 1 n n+1 ADDRESS t t SW HW R/W t t HCLD SCLD CNTLD CNTINC t t A SCRST HCRST n+2 CNTRST t t SD HD DATA D IN 0 DATA Q Q Q OUT 0 1 n Counter Write Read Read Read Reset Address 0 Address 0 Address 1 Address n Notes: 26. CE = LB = UB = V ; CE = MRST = MKLD = MKRD = CNTRD = V . 0 IL 1 IH 27. No dead cycle exists during counter reset. A Read or W
ページ18に含まれる内容の要旨
CY7C0430BV CY7C0430CV Switching Waveforms (continued) [28] Load and Read Address Counter t CYC2 t t CH2 CL2 Note 29 Note 30 CLK t t t HA CA2 SA t t CKHZ CKLZ A –A [31] 0 15 A A n n+2 t t SCLD HCLD CNTLD CNTINC t SCINC t HCINC t t SCRD HCRD CNTRD INTERNAL A A A A A n n+1 n+2 n+2 n+2 ADDRESS t DC t t CD2 t CKLZ CKHZ DATA OUT Q Q Q Q Q n+2 Q x–1 x n n+1 n+2 Load Read Data with Counter Read External Internal Address Address Notes: 28. CE = OE = LB = UB = V ; CE = R/W = CNTRST = MRST = MKLD = MK
ページ19に含まれる内容の要旨
CY7C0430BV CY7C0430CV Switching Waveforms (continued) [32] Load and Read Mask Register t CYC2 t t CH2 CL2 Note 29 Note 30 CLK t t t HA CA2 SA t t CKHZ CKLZ A –A [33] 0 15 A A n n t t SMLD HMLD MKLD t t SMRD HMRD MKRD MASK INTERNAL A A A A A n n n n n VALUE Load Read Mask Register Mask Register Value Value Notes: 32. CE = OE = LB = UB = V ; CE = R/W = CNTRST = MRST = CNTLD = CNTRD = CNTINC =V . 0 IL 1 IH 33. This is the value of the Mask Register read out on the address lines. Document #:
ページ20に含まれる内容の要旨
CY7C0430BV CY7C0430CV Switching Waveforms (continued) [34, 35, 36] Port 1 Write to Port 2 Read t CYC2 t t CH2 CL2 CLK P1 t HA t SA PORT-1 A ADDRESS n t t SW HW R/W P1 t CKHZ t SD t HD t CKLZ PORT-1 D n DATA IN t CCS t CYC2 t CL2 CLK P2 t CH2 t t SA HA PORT-2 A ADDRESS n R/W P2 t CD2 PORT-2 Q n DATA OUT t DC Notes: 34. CE = OE = LB = UB = CNTLD =V ; CE = CNTRST = MRST = MKLD = MKRD = CNTRD = CNTINC =V . 0 IL 1 IH 35. This timing is valid when one port is writing, and one or more of the three
