ページ1に含まれる内容の要旨
CY7C1012DV33
12-Mbit (512K X 24) Static RAM
Features Functional Description
■ High speed The CY7C1012DV33 is a high performance CMOS static RAM
organized as 512K words by 24 bits. Each data byte is separately
❐ t = 10 ns
AA
controlled by the individual chip selects (CE , CE , and CE ).
1 2 3
■ Low active power
CE controls the data on the I/O – I/O , while CE controls the
1 0 7 2
❐ I = 175 mA at 10 ns
data on I/O – I/O , and CE controls the data on the data pins
CC
8 15 3
I/O – I/O . This device
ページ2に含まれる内容の要旨
CY7C1012DV33 Selection Guide Description –10 Unit Maximum Access Time 10 ns Maximum Operating Current 175 mA Maximum CMOS Standby Current 25 mA Pin Configuration [1] Figure 1. 119-Ball PBGA (Top View) 1 2 3 4 5 6 7 A NC AAAAA NC B NC A A CE AA NC 1 C I/O NC CE NC CE NC I/O 12 2 3 0 D I/O V V V V V I/O 13 DD SS SS SS DD 1 E I/O V V V V V I/O 14 SS DD SS DD SS 2 F I/O V V V V V I/O 15 DD SS SS SS DD 3 G I/O V V V V V I/O 16 SS DD SS DD SS 4 H I/O V V V V V I/O 17 DD SS SS SS DD 5 J NC V V V V V
ページ3に含まれる内容の要旨
CY7C1012DV33 Current into Outputs (LOW) ........................................ 20 mA Maximum Ratings Static Discharge Voltage............. ...............................>2001V Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. (MIL-STD-883, Method 3015) Storage Temperature ................................. –65 °C to +150 °C Latch Up Current ..................................................... >200 mA Ambient Temperature with Operating R
ページ4に含まれる内容の要旨
CY7C1012DV33 Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description Test Conditions Max Unit C Input Capacitance T = 25 °C, f = 1 MHz, V = 3.3V 8 pF IN A CC C I/O Capacitance 10 pF OUT Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. 119-Ball Parameter Description Test Conditions Unit PBGA Θ Thermal Resistance Still air, soldered on a 3 × 4.5 inch, 20.31 °C/W JA (j
ページ5に含まれる内容の要旨
CY7C1012DV33 AC Switching Characteristics [5] Over the Operating Range –10 Parameter Description Unit Min Max Read Cycle [6] t V (Typical) to the First Access 100 μs power CC t Read Cycle Time 10 ns RC t Address to Data Valid 10 ns AA t Data Hold from Address Change 3 ns OHA [3] t CE Active LOW to Data Valid 10 ns ACE t OE LOW to Data Valid 5 ns DOE [7] t OE LOW to Low Z 1ns LZOE [7] t OE HIGH to High Z 5ns HZOE [3, 7] t CE Active LOW to Low Z 3ns LZCE [3, 7] t CE Deselect HIGH to High Z 5ns
ページ6に含まれる内容の要旨
CY7C1012DV33 Data Retention Characteristics Over the Operating Range [3] Parameter Description Conditions Min Typ Max Unit V V for Data Retention 2 V DR CC I Data Retention Current V = 2V, CE > V – 0.2V, 25 mA CCDR CC CC V > V – 0.2V or V < 0.2V IN CC IN [11] t Chip Deselect to Data Retention 0ns CDR Time [12] Operation Recovery Time t ns t R RC Data Retention Waveform DATA RETENTION MODE V 3.0V 3.0V V > 2V CC DR t t CDR R CE Switching Waveforms [13, 14] Figure 3. Read Cycle No. 1 tRC RC ADD
ページ7に含まれる内容の要旨
CY7C1012DV33 Switching Waveforms (continued) [3, 16, 17] Figure 5. Write Cycle No. 1 (CE Controlled) t WC ADDRESS t SCE CE t t SA SCE t t AW HA t PWE WE t t SD HD DATA I/O DATA VALID [3, 16, 17] Figure 6. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE OE t SD t t HD HZOE DATA VALID DATA I/O IN NOTE 18 [3, 17] Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE t t SD HD NOTE 18 DATA I/O DA
ページ8に含まれる内容の要旨
CY7C1012DV33 Truth Table CE CE CE OE WE I/O – I/O I/O – I/O I/O – I/O Mode Power 1 2 3 0 7 8 15 16 23 H H H X X High Z High Z High Z Power Down Standby (I ) SB L H H L H Data Out High Z High Z Read Active (I ) CC ) H L H L H High Z Data Out High Z Read Active (I CC H H L L H High Z High Z Data Out Read Active (I ) CC LLLL H Full Data Out Full Data Out Full Data Out Read Active (I ) CC ) L H H X L Data In High Z High Z Write Active (I CC H L H X L High Z Data In High Z Write Active (I ) CC H H L
ページ9に含まれる内容の要旨
CY7C1012DV33 Ordering Information Speed Package Operating Ordering Code Package Type (ns) Name Range 10 CY7C1012DV33-10BGXI 51-85115 119-Ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-Free) Industrial Package Diagram Figure 8. 119-Ball PBGA (14 x 22 x 2.4 mm) 51-85115-*B Document Number: 38-05610 Rev. *D Page 9 of 11 [+] Feedback
ページ10に含まれる内容の要旨
CY7C1012DV33 Document History Page Document Title: CY7C1012DV33 12-Mbit (512K X 24) Static RAM Document Number: 38-05610 Orig. of Submission Rev. ECN No. Description of Change Change Date ** 250650 SYT See ECN New data sheet *A 469517 NXR See ECN Converted from Advance Information to Preliminary Corrected typo in the Document Title Removed –10 and –12 speed bins from product offering Changed J7 Ball of BGA from DNU to NC Removed Industrial Operating range from product offering Included the Max
ページ11に含まれる内容の要旨
CY7C1012DV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Solutions PSoC psoc.cypress.com General psoc.cypress.com/solutions Clocks & Buffers clocks.cypress.com Low Power/Low Voltage psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog psoc.cypress.c
