ページ1に含まれる内容の要旨
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
3.3V 32K/64K x 16/18 Dual-Port Static
RAM
■ Fully asynchronous operation
Features
■ Automatic power down
■ True Dual-Ported memory cells which allow
■ Expandable data bus to 32/36 bits or more using Master/Slave
simultaneous access of the same memory location
chip select when using more than one device
[1]
■ 32K x 16 organization (CY7C027V/027VN/027AV )
■ On-chip arbitration logic
■ 64K x 16 organization (CY7C028V)
■ Semaphores included to permit s
ページ2に含まれる内容の要旨
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Pin Configurations Figure 1. 100-Pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A9L 1 75 A9R A10L 2 74 A10R A11L 3 73 A11R 72 A12R A12L 4 A13L 5 71 A13R A14L 6 70 A14R [1] A15L 7 69 A15R [1] NC 8 68 NC NC 9 67 NC LBL 10 66 LBR UBL 11 65 UBR CE0L 12 64 CE0R CY7C028V (64K x 16) CE1L 13 63 CE1R SEML 14 62 SEMR CY7C027V/027VN/027AV (32K x 16) VCC 15 61 GND R/WL 16 60 R/WR OEL 17 59 OER GND 18 58 G
ページ3に含まれる内容の要旨
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Pin Configurations (continued) Figure 2. 100-Pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 A8R A9L 1 A10L 2 74 A9R A11L 3 73 A10R 72 A11R A12L 4 A13L 5 71 A12R A14L 6 70 A13R [2] A15L 7 69 A14R LBL 8 68 A15R [2] UBL 9 67 LBR CE0L 10 66 UBR CE1L 11 65 CE0R SEML 12 64 CE1R CY7C038V (64K x 18) R/WL 13 63 SEMR OEL 14 62 R/WR CY7C037V/037AV (32K x 18) VCC 15 61 GND GND 16 60 OER I/O17L 17 59 GND
ページ4に含まれる内容の要旨
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Pin Definitions Left Port Right Port Description CE , CE CE , CE Chip Enable (CE is LOW when CE ≤ V and CE ≥ V ) 0L 1L 0R 1R 0 IL 1 IH R/W R/W Read/Write Enable L R OE OE Output Enable L R A –A A –A Address (A –A for 32K; A –A for 64K devices) 0L 15L 0R 15R 0 14 0 15 I/O –I/O I/O –I/O Data Bus Input/Output (I/O –I/O for x16 devices; I/O –I/O for x18) 0L 17L 0R 17R 0 15 0 17 SEM SEM Semaphore Enable L R UB UB Upper Byte Select (I/O –I/O for x16 device
ページ5に含まれる内容の要旨
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V generated to the owner. The interrupt is reset when the owner are used to reserve resources that are shared between the two reads the contents of the mailbox. The message is user defined. ports.The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given Each port can read the other port’s mailbox without resetting the resource, it sets a latch by writing a zero to a semaphore location. interr
ページ6に含まれる内容の要旨
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V [2] DC Input Voltage .................................. –0.5V to V +0.5V Maximum Ratings CC Output Current into Outputs (LOW)............................. 20 mA Exceeding maximum ratings may shorten the useful life of the Static Discharge Voltage.......................................... > 1100V device. User guidelines are not tested. Latch-up Current.................................................... > 200 mA Storage Temperature ...................
ページ7に含まれる内容の要旨
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Figure 3. AC Test Loads and Waveforms 3.3V 3.3V R = 250Ω R1 = 590Ω TH OUTPUT OUTPUT R1 = 590Ω OUTPUT C= 30 pF C= 30 pF R2 = 435Ω C= 5pF R2 = 435Ω V =1.4V TH (a) Normal Load (Load 1) (c) Three-State Delay(Load 2) (b) Thévenin Equivalent (Load 1) (Used for t , t , t , & t LZ HZ HZWE LZWE including scope and jig) ALL INPUTPULSES 3.0V 90% 90% 10% 10% GND 3 ns ≤3ns ≤ [6] Switching Characteristics Over the Operating Range CY7C027V/027VN/027AV/028V/ CY7C03
ページ8に含まれる内容の要旨
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V [6] Switching Characteristics Over the Operating Range (continued) CY7C027V/027VN/027AV/028V/ CY7C037V/037AV/038V Parameter Description Unit -15 -20 -25 Min Max Min Max Min Max t Data Hold From Write End 0 0 0 ns HD [9, 10] t R/W LOW to High Z 10 12 15 ns HZWE [9 ,10] t R/W HIGH to Low Z 3 3 3 ns LZWE [36] t Write Pulse to Data Delay 30 40 50 ns WDD [36] t Write Data Valid to Read Data Valid 25 30 35 ns DDD [11] Busy Timing t BUSY LOW from Address Ma
ページ9に含まれる内容の要旨
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Switching Waveforms [15, 16, 17] Figure 4. Read Cycle No. 1 (Either Port Address Access) t RC ADDRESS t AA t t OHA OHA DATA OUT PREVIOUS DATA VALID DATA VALID [15, 18, 19] Figure 5. Read Cycle No. 2 (Either Port CE/OE Access) t ACE CE and LB or UB t HZCE t DOE OE t HZOE t LZOE DATA VALID DATA OUT t LZCE t PU t PD I CC CURRENT I SB [15, 17, 18, 19] Figure 6. Read Cycle No. 3 (Either Port) t RC ADDRESS t t AA OHA UB or LB t HZCE t LZCE t ABE CE t HZ
ページ10に含まれる内容の要旨
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Switching Waveforms(continued) [20, 21, 22, 23] Figure 7. Write Cycle No. 1: R/W Controlled Timing t WC ADDRESS [26] t HZOE OE t AW [24,25] CE [23] t t t SA PWE HA R/W [26] t HZWE t LZWE NOTE 27 NOTE 27 DATAOUT t t SD HD DATA IN [20, 21, 22, 28] Figure 8. Write Cycle No. 2: CE Controlled Timing t WC ADDRESS t AW [24,25] CE t t t SA SCE HA R/W t t SD HD DATA IN Notes 20. R/W must be HIGH during all address transitions. 21. A write occurs during the
ページ11に含まれる内容の要旨
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Switching Waveforms(continued) [29] Figure 9. Semaphore Read After Write Timing, Either Side t t SAA OHA A –A VALID ADRESS VALID ADRESS 0 2 t AW t ACE t HA SEM t t SCE SOP t SD I/O 0 DATA VALID DATA VALID IN OUT t HD t t SA PWE R/W t t SWRD DOE t OE SOP WRITE CYCLE READ CYCLE [30, 31, 32] Figure 10. Timing Diagram of Semaphore Contention A –A 0L 2L MATCH R/W L SEM L t SPS A –A 0R 2R MATCH R/W R SEM R Notes 29. CE = HIGH for the duration of the abov
ページ12に含まれる内容の要旨
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Switching Waveforms(continued) [33] Figure 11. Timing Diagram of Read with BUSY (M/S=HIGH) t WC ADDRESS R MATCH t PWE R/W R t t SD HD DATA IN VALID R t PS ADDRESS L MATCH t BLA t BHA BUSY L t BDD t DDD DATA VALID OUTL t WDD Figure 12. Write Timing with Busy Input (M/S=LOW) t PWE R/W t t WB WH BUSY Note 33. CE = CE = LOW. L R Document #: 38-06078 Rev. *B Page 12 of 18 [+] Feedback
ページ13に含まれる内容の要旨
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Switching Waveforms(continued) [34] Figure 13. Busy Timing Diagram No. 1 (CE Arbitration) CE Valid First: L ADDRESS L,R ADDRESS MATCH CE L t PS CE R t t BLC BHC BUSY R CE ValidFirst: R ADDRESS ADDRESS MATCH L,R CE R t PS CE L t t BLC BHC BUSY L [34] Figure 14. Busy Timing Diagram No. 2 (Address Arbitration) Left Address Valid First: t or t RC WC ADDRESS L ADDRESS MATCH ADDRESS MISMATCH t PS ADDRESS R t t BLA BHA BUSY R Right Address Valid First: t
ページ14に含まれる内容の要旨
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Switching Waveforms(continued) Figure 15. Interrupt Timing Diagrams Left Side Sets INT : R t WC ADDRESS WRITE 7FFF (FFFF for CY7C028V/38V) L [35] t HA CE L R/W L INT R [36] t INS Right Side Clears INT : R t RC READ 7FFF ADDRESS R (FFFF for CY7C028V/38V) CE R [36] t INR R/W R OE R INT R Right Side Sets INT : L t WC ADDRESS R WRITE 7FFE (FFFE for CY7C028V/38V) [35] t HA CE R R/W R INT L [36] t INS Left Side Clears INT : L t RC READ 7FFE ADDRESS R (FFF
ページ15に含まれる内容の要旨
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Table 1. Non-Contending Read/Write Inputs Outputs CE R/W OE UB LB SEM I/O –I/O I/O –I/O Operation 9 17 0 8 H X X X X H High Z High Z Deselected: Power Down X X X H H H High Z High Z Deselected: Power Down L L X L H H Data In High Z Write to Upper Byte Only L L X H L H High Z Data In Write to Lower Byte Only L L X L L H Data In Data In Write to Both Bytes L H L L H H Data Out High Z Read Upper Byte Only L H L H L H High Z Data Out Read Lower Byte On
ページ16に含まれる内容の要旨
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Ordering Information 32K x16 3.3V Asynchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 15 CY7C027V-15AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C027V-15AXC A100 100-Pin Pb-Free Thin Quad Flat Pack Commercial CY7C027VN-15AXC A100 100-Pin Pb-Free Thin Quad Flat Pack Commercial 20 CY7C027V-20AC A100 100-Pin Thin Quad Flat Pack Commercial CY7C027V-20AXC A100 100-Pin Pb-Free Thin Quad Flat Pack Commercial 2
ページ17に含まれる内容の要旨
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Package Diagram Figure 16. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100 51-85048-*C Document #: 38-06078 Rev. *B Page 17 of 18 [+] Feedback
ページ18に含まれる内容の要旨
CY7C027V/027VN/027AV/028V CY7C037V/037AV/038V Document History Page Document Title: CY7C027V/027VN/027AV/CY7C028V/037V/037AV/038V 3.3V 32K/64K x 16/18 Dual Port Static RAM Document Number: 38-06078 Orig. of Submission Rev. ECN No. Description of Change Change Date ** 237626 YDT 6/30/04 Converted data sheet from old spec 38-00670 to conform with new data sheet. Removed cross information from features section *A 259110 JHX See ECN Added Pb-Free packaging information. *B 2623540 VKN/PYRS 12/17/08
