ページ1に含まれる内容の要旨
CY7C024AV/024BV/025AV/026AV
CY7C0241AV/0251AV/036AV
3.3V 4K/8K/16K x 16/18 Dual-Port
Static RAM
■ Fully asynchronous operation
Features
■ Automatic power down
■ True dual-ported memory cells which enable simultaneous
access of the same memory location
■ Expandable data bus to 32 bits, 36 bits or more using Master
and Slave chip select when using more than one device
■ 4, 8 or 16K × 16 organization
■ On chip arbitration logic
[1]
■ (CY7C024AV/024BV / 025AV/026AV)
■ Semaphores included to per
ページ2に含まれる内容の要旨
CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Pin Configurations Figure 1. 100-Pin TQFP (Top View) 100 9998 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 NC 1 NC 74 NC NC 2 73 NC NC 3 NC 72 NC 4 A 71 5L IO 10L 5 70 A 4L IO 11L 6 69 A 3L IO 12L 7 68 A 2L IO 13L 8 A 67 1L GND 9 A 66 0L IO 14L 10 INT L 65 IO 15L 11 BUSY L 64 12 V GND CC 63 CY7C024AV/024BV (4K × 16) 13 GND M/S 62 IO 14 0R BUSY 61 R CY7C025AV (8K × 16) IO 1R 15 INT 60 R IO 2R 16 59 A 0R V CC 17 58 A
ページ3に含まれる内容の要旨
CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Pin Configurations (continued) Figure 2. 100-Pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 NC 1 NC 74 NC NC 2 NC 73 IO 8L 3 NC 72 IO 4 17L 71 A 5L IO 11L 5 A 70 4L IO 12L 6 69 A 3L IO 13L 7 68 A 2L IO 14L 8 A 67 1L GND 9 A 66 0L IO 15L 10 INT L 65 IO 16L 11 BUSY L 64 12 V GND CC 63 CY7C0241AV (4K × 18) GND 13 M/S 62 IO 14 0R BUSY 61 R CY7C0251AV (8K × 18) IO 1R 15 INT 60 R IO 2R 16 A 59 0R
ページ4に含まれる内容の要旨
CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Pin Configurations (continued) Figure 3. 100-Pin TQFP (Top View) 100 9998 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 NC 1 NC 74 NC NC 2 73 NC IO 8L 3 A 13L 72 IO 17L 4 71 A 5L IO 11L 5 70 A 4L IO 12L 6 69 A 3L IO 13L 7 68 A 2L IO 14L 8 A 67 1L GND 9 A 66 0L IO 15L 10 INT L 65 IO 16L 11 BUSY L 64 12 V GND CC 63 CY7C036AV (16K × 18) 13 GND M/S 62 IO 14 0R BUSY 61 R IO INT 1R 15 60 R IO 2R 16 59 A 0R V CC 17 58 A 1R IO
ページ5に含まれる内容の要旨
CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Pin Definitions Left Port Right Port Description CE CE Chip Enable L R R/W R/W Read and Write Enable L R OE OE Output Enable L R A –A A –A Address (A –A for 4K devices; A –A for 8K devices; A –A for 16K) 0L 13L 0R 13R 0 11 0 12 0 13 IO –IO IO –IO Data Bus Input and Output 0L 17L 0R 17R SEM SEM Semaphore Enable L R UB UB Upper Byte Select (IO –IO for x16 devices; IO –IO for x18 devices) L R 8 15 9 17 LB LB Lower Byte Select (IO –IO for x16 dev
ページ6に含まれる内容の要旨
CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV 3FFF for the CY7C026AV/36AV) is the mailbox for the right port Semaphore Operation and the second highest memory location (FFE for the The CY7C024AV/024BV/025AV/026AV and CY7C024AV/024BV/41AV/1FFE for the CY7C025AV/51AV, CY7C0241AV/0251AV/036AV provide eight semaphore latches, 3FFE for the CY7C026AV/36AV) is the mailbox for the left port. which are separate from the dual port memory locations. When one port writes to the other port’s mailbox,
ページ7に含まれる内容の要旨
CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Table 1. Non-Contending Read/Write Inputs Outputs Operation CE R/W OE UB LB SEM IO –IO IO –IO 9 17 0 8 H X X X X H High Z High Z Deselected: Power Down X X X H H H High Z High Z Deselected: Power Down L L X L H H Data In High Z Write to Upper Byte Only L L X H L H High Z Data In Write to Lower Byte Only L L X L L H Data In Data In Write to Both Bytes L H L L H H Data Out High Z Read Upper Byte Only L H L H L H High Z Data Out Read Lower B
ページ8に含まれる内容の要旨
CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV [15] DC Input Voltage ............................... –0.5V to V + 0.5V Maximum Ratings CC Output Current into Outputs (LOW)............................. 20 mA [14] Exceeding maximum ratings may shorten the useful life of the Static Discharge Voltage.......................................... > 2001V device. User guidelines are not tested. Latch-up Current.................................................... > 200 mA Storage Temperature ......
ページ9に含まれる内容の要旨
CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Figure 4. AC Test Loads and Waveforms 3.3V 3.3V R = 250Ω R1 = 590Ω TH OUTPUT OUTPUT R1 = 590Ω OUTPUT C= 30pF C= 30 pF R2 = 435Ω C= 5pF R2 = 435Ω V =1.4V TH (a) Normal Load (Load 1) (c) Three-State Delay (Load 2) (b) Thévenin Equivalent (Load 1) (Used for t , t , t , and t LZ HZ HZWE LZWE ALL INPUTPULSES including scope and jig) 3.0V 90% 90% 10% 10% GND 3ns ≤ 3 ns ≤ Switching Characteristics [20] Over the Operating Range CY7C024AV/024BV/025A
ページ10に含まれる内容の要旨
CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Switching Characteristics [20] Over the Operating Range (continued) CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Parameter Description Unit -20 -25 Min Max Min Max t Write Pulse Width 15 20 ns PWE t Data Setup to Write End 15 15 ns SD t Data Hold From Write End 0 0 ns HD [23, 24] t R/W LOW to High Z 12 15 ns HZWE [23, 24] t R/W HIGH to Low Z 3 0 ns LZWE [25] t Write Pulse to Data Delay 45 50 ns WDD [25] t Write Data Valid to Read Data
ページ11に含まれる内容の要旨
CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Switching Waveforms [29, 30, 31] Figure 5. Read Cycle No. 1 (Either Port Address Access) t RC ADDRESS t AA t t OHA OHA DATA OUT PREVIOUS DATA VALID DATA VALID [29, 32, 33] Figure 6. Read Cycle No. 2 (Either Port CE/OE Access) t ACE CE and LB or UB t HZCE t DOE OE t HZOE t LZOE DATA VALID DATA OUT t LZCE t PU t PD I CC CURRENT I SB [29, 31, 32, 33] Figure 7. Read Cycle No. 3 (Either Port) t RC ADDRESS t t AA OHA UB or LB t HZCE t LZCE t ABE
ページ12に含まれる内容の要旨
CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Switching Waveforms (continued) [34, 35, 36, 37] Figure 8. Write Cycle No. 1: R/W Controlled Timing t WC ADDRESS [40] t HZOE OE t AW [38, 39] CE [37] t t t SA PWE HA R/W [40] t HZWE t LZWE NOTE 41 NOTE 41 DATAOUT t t SD HD DATA IN [34, 35, 36, 42] Figure 9. Write Cycle No. 2: CE Controlled Timing t WC ADDRESS t AW [38, 39] CE t t t SA SCE HA R/W t t SD HD DATA IN Notes 34. R/W or CE must be HIGH during all address transitions. 35. A write o
ページ13に含まれる内容の要旨
CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Switching Waveforms (continued) [43] Figure 10. Semaphore Read After Write Timing, Either Side t t SAA OHA A –A VALID ADRESS VALID ADRESS 0 2 t AW t ACE t HA SEM t t SCE SOP t SD IO 0 DATA VALID DATA VALID IN OUT t HD t t SA PWE R/W t t SWRD DOE t OE SOP WRITE CYCLE READ CYCLE [44, 45, 46] Figure 11. Timing Diagram of Semaphore Contention A –A 0L 2L MATCH R/W L SEM L t SPS A –A 0R 2R MATCH R/W R SEM R Notes 43. CE = HIGH for the duration of
ページ14に含まれる内容の要旨
CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Switching Waveforms (continued) [47] Figure 12. Timing Diagram of Read with BUSY (M/S=HIGH) t WC ADDRESS R MATCH t PWE R/W R t t SD HD DATA IN VALID R t PS ADDRESS L MATCH t BLA t BHA BUSY L t BDD t DDD DATA VALID OUTL t WDD Figure 13. Write Timing with Busy Input (M/S=LOW) t PWE R/W t t WB WH BUSY Note 47. CE = CE = LOW. L R Document #: 38-06052 Rev. *J Page 14 of 19 [+] Feedback
ページ15に含まれる内容の要旨
CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Switching Waveforms (continued) [48] Figure 14. Busy Timing Diagram No.1 (CE Arbitration) CE Valid First L ADDRESS L,R ADDRESS MATCH CE L t PS CE R t t BLC BHC BUSY R CE ValidFirst: R ADDRESS ADDRESS MATCH L,R CE R t PS CE L t t BLC BHC BUSY L [48] Figure 15. Busy Timing Diagram No.2 (Address Arbitration) Left Address Valid First: t or t RC WC ADDRESS L ADDRESS MATCH ADDRESS MISMATCH t PS ADDRESS R t t BLA BHA BUSY R Right Address Valid Fir
ページ16に含まれる内容の要旨
CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Switching Waveforms (continued) Figure 16. Interrupt Timing Diagram Left Side Sets INT : R t WC ADDRESS WRITE 1FFF (OR 1/3FFF) L [49] t HA CE L R/W L INT R [50] t INS Right Side Clears INT : R t RC READ 7FFF ADDRESS R (OR 1/3FFF) CE R [50] t INR R/W R OE R INT R Right Side Sets INT : L t WC ADDRESS R WRITE 1FFE (OR 1/3FFE) [49] t HA CE R R/W R INT L [50] t INS Left Side Clears INT : L t RC READ 7FFE ADDRESS R OR 1/3FFE) CE L [50] t INR R/W L
ページ17に含まれる内容の要旨
CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Ordering Information 4K x16 3.3V Asynchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Diagram Package Type Range 15 CY7C024AV-15AI 51-85048 100-Pin Thin Quad Flat Pack Industrial CY7C024BV-15AXI 51-85048 100-Pin Pb-Free Thin Quad Flat Pack 20 CY7C024AV-20AC 51-85048 100-Pin Thin Quad Flat Pack Commercial CY7C024AV-20AXC 51-85048 100-Pin Pb-Free Thin Quad Flat Pack CY7C024AV-20AI 51-85048 100-Pin Thin Quad Flat Pack Ind
ページ18に含まれる内容の要旨
CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV 16K x18 3.3V Asynchronous Dual-Port SRAM Speed Package Operating (ns) Ordering Code Name Package Type Range 20 CY7C036AV-20AC 51-85048 100-Pin Thin Quad Flat Pack Commercial 25 CY7C036AV-25AC 51-85048 100-Pin Thin Quad Flat Pack Commercial CY7C036AV-25AXC 51-85048 100-Pin Pb-free Thin Quad Flat Pack CY7C036AV-25AI 51-85048 100-Pin Thin Quad Flat Pack Industrial Package Diagram Figure 17. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A10
ページ19に含まれる内容の要旨
CY7C024AV/024BV/025AV/026AV CY7C0241AV/0251AV/036AV Document History Page Document Title: CY7C024AV/024BV/025AV/026AV, CY7C0241AV/0251AV/036AV 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM Document Number: 38-06052 Orig. of Submission Rev. ECN No. Description of Change Change Date ** 110204 SZV 11/11/01 Change from Spec number: 38-00838 to 38-06052 *A 122302 RBI 12/27/02 Power up requirements added to Maximum Ratings Information *B 128958 JFU 9/03/03 Added CY7C025AV-25AI to Ordering Information
