ページ1に含まれる内容の要旨
CY62128EV30
MoBL® 1 Mbit (128K x 8) Static RAM
Features Functional Description
[1]
■ Very high speed: 45 ns The CY62128EV30 is a high performance CMOS static RAM
module organized as 128K words by 8 bits. This device features
❐ Temperature ranges:
advanced circuit design to provide ultra low active current. This
• Industrial: –40°C to +85°C
®
is ideal for providing More Battery Life™ (MoBL ) in portable
• Automotive-A: –40°C to +85°C
applications such as cellular telephones. The device also has a
ページ2に含まれる内容の要旨
CY62128EV30 [2] Pin Configuration A 1 11 32 OE A 24 OE 11 25 2 A 31 A 23 9 A A 10 26 9 10 A 3 30 CE A 22 8 27 26 CE 1 8 1 4 A 29 A 28 13 IO 21 IO 7 13 7 5 28 29 20 WE IO WE IO 6 6 CE 6 30 27 IO CE 19 IO 2 5 2 5 A 7 TSOP I A 31 STSOP 15 26 IO 18 IO 4 15 4 V 8 Top View 25 IO V 32 Top View 17 IO CC 3 CC 3 (not to scale) 24 (not to scale) 16 NC 9 GND NC 1 GND A 23 IO A 15 IO 16 10 2 2 16 2 22 14 IO A IO A 3 11 1 14 1 14 A 21 IO A 13 IO 12 4 12 0 12 0 A 20 A A 12 A 7 13 0 5 7 0 A A 14 19 A A 6 11
ページ3に含まれる内容の要旨
CY62128EV30 Output Current into Outputs (LOW)............................. 20 mA Maximum Ratings Static Discharge Voltage.......................................... > 2001V Exceeding maximum ratings may impair the useful life of the (MIL-STD-883, Method 3015) device. These user guidelines are not tested. Latch up Current..................................................... > 200 mA Storage Temperature.................................. –65°C to +150°C Ambient Temperature with Operating Range Power
ページ4に含まれる内容の要旨
CY62128EV30 Capacitance [8] (For all packages) Parameter Description Test Conditions Max Unit C Input Capacitance T = 25°C, f = 1 MHz, 10 pF IN A V = V CC CC(typ) C Output Capacitance 10 pF OUT Thermal Resistance Parameter Description Test Conditions TSOP I SOIC STSOP Unit Θ Thermal Resistance Still Air, soldered on a 3 x 4.5 inch, 33.01 48.67 32.56 °C/W JA (Junction to Ambient) two-layer printed circuit board Θ Thermal Resistance 3.42 25.86 3.59 °C/W JC (Junction to Case) Figure 1. AC Test Lo
ページ5に含まれる内容の要旨
CY62128EV30 [10] Data Retention Waveform DATA RETENTION MODE V V CC(min) V > 1.5V CC(min) V DR CC t t CDR R CE Switching Characteristics [10, 11] (Over the Operating Range) 45 ns (Ind’l/Auto-A) 55 ns (Auto-E) Parameter Description Unit Min Max Min Max Read Cycle t Read Cycle Time 45 55 ns RC t Address to Data Valid 45 55 ns AA t Data Hold from Address Change 10 10 ns OHA t CE LOW to Data Valid 45 55 ns ACE t OE LOW to Data Valid 22 25 ns DOE [12] t OE LOW to Low Z 55 ns LZOE [12,13] t OE HIGH
ページ6に含まれる内容の要旨
CY62128EV30 Switching Waveforms [15, 16] Figure 2. Read Cycle 1 (Address transition controlled) tRC RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID [10, 16, 17] Figure 3. Read Cycle No. 2 (OE controlled) ADDRESS t RC CE t ACE OE t HZOE t DOE t HZCE t LZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID DATA OUT t LZCE t PD t I V PU CC CC SUPPLY 50% 50% CURRENT I SB [10, 15, 18, 19] Figure 4. Write Cycle No. 1 (WE controlled) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE OE t SD t H
ページ7に含まれる内容の要旨
CY62128EV30 Switching Waveforms (continued) [10, 14, 18, 19] Figure 5. Write Cycle No. 2 (CE1 or CE2 controlled) t WC ADDRESS t SCE CE t SA t t AW HA t PWE WE t t SD HD DATA IO DATA VALID [10, 19] Figure 6. Write Cycle No. 3 (WE controlled, OE LOW) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE t t SD HD 20 NOTE DATA VALID DATA IO t t LZWE HZWE Table 2. Truth Table for CY62128EV30 CE CE WE OE Inputs/Outputs Mode Power 1 2 H X X X High Z Deselect/Power Down Standby (I ) SB X L X X High Z De
ページ8に含まれる内容の要旨
CY62128EV30 Ordering Information Speed Package Operating Ordering Code Package Type (ns) Diagram Range 45 CY62128EV30LL-45SXI 51-85081 32-pin 450-Mil SOIC (Pb-free) Industrial CY62128EV30LL-45ZXI 51-85056 32-pin TSOP Type I (Pb-free) CY62128EV30LL-45ZAXI 51-85094 32-pin STSOP (Pb-free) 45 CY62128EV30LL-45ZXA 51-85056 32-pin TSOP Type I (Pb-free) Automotive-A 55 CY62128EV30LL-55ZXE 51-85056 32-pin TSOP Type I (Pb-free) Automotive-E Contact your local Cypress sales representative for availability
ページ9に含まれる内容の要旨
CY62128EV30 Package Diagrams (continued) Figure 8. 32-Pin Thin Small Outline Package Type I (8 x 20 mm), 51-85056 51-85056-*D Document #: 38-05579 Rev. *D Page 9 of 11 [+] Feedback
ページ10に含まれる内容の要旨
CY62128EV30 Package Diagrams (continued) Figure 9. 32-Pin Shrunk Thin Small Outline Package (8 x 13.4 mm), 51-85094 51-85094-*D Document #: 38-05579 Rev. *D Page 10 of 11 [+] Feedback
ページ11に含まれる内容の要旨
CY62128EV30 Document History Page Document Title: CY62128EV30 MoBL® 1 Mbit (128K x 8) Static RAM Document Number: 38-05579 REV. ECN NO. Issue Date Orig. of Description of Change Change ** 285473 See ECN PCI New Data Sheet *A 461631 See ECN NXR Converted from Preliminary to Final Removed 35 ns Speed Bin Removed “L” version of CY62128EV30 Removed Reverse TSOP I package from Product offering. Changed I from 8 mA to 11 mA and I from 12 mA to 16 mA for f = f CC (Typ) CC (Max) max Changed I from 1.5 m
