ページ1に含まれる内容の要旨
®
CY62157EV18 MoBL
8-Mbit (512K x 16) Static RAM
deselected (CE HIGH or CE LOW or both BHE and BLE are
Features
1 2
HIGH). The input and output pins (IO through IO ) are
0 15
• Very high speed: 55 ns
placed in a high impedance state when:
• Wide voltage range: 1.65V–2.25V
• Deselected (CE HIGH or CE LOW)
1 2
• Pin Compatible with CY62157DV18 and CY62157DV20
• Outputs are disabled (OE HIGH)
• Ultra low standby power
• Both Byte High Enable and Byte Low Enable are disabled
— Typical Standby curr
ページ2に含まれる内容の要旨
® CY62157EV18 MoBL Logic Block Diagram DATA IN DRIVERS A 10 A 9 A 8 A 7 A 6 512K x 16 A 5 RAM Array IO –IO A 0 7 4 A 3 IO –IO 8 15 A 2 A 1 A 0 COLUMN DECODER BHE WE CE 2 CE 1 OE BLE POWER DOWN CE BHE CIRCUIT 2 CE BLE 1 [3] Pin Configuration 48-ball VFBGA Top View 126 3 4 5 A A A CE OE A BLE 0 1 2 2 IO BHE A A CE B IO 8 3 4 1 0 C IO IO A A IO IO 10 5 6 1 2 9 V IO A IO V D A SS 11 7 3 CC 17 V IO NC A IO V E CC 12 16 4 SS IO IO A A IO IO 14 F 14 13 15 5 6 IO NC A A IO WE 15 12 13 7 G A A A A A NC
ページ3に含まれる内容の要旨
® CY62157EV18 MoBL [4, 5] Maximum Ratings DC Input Voltage ......... –0.2V to 2.45V (V + 0.2V) CCmax Output Current into Outputs (LOW) ............................ 20 mA Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static Discharge Voltage ......................................... > 2001V Storage Temperature ................................ –65°C to + 150°C (in accordance with MIL-STD-883, Method 3015) Ambient Temperature with Latch-
ページ4に含まれる内容の要旨
® CY62157EV18 MoBL [8] Thermal Resistance Parameter Description Test Conditions BGA Unit Θ Thermal Resistance Still air, soldered on a 3 × 4.5 inch, 72 °C/W JA (Junction to Ambient) two-layer printed circuit board Θ Thermal Resistance 8.86 °C/W JC (Junction to Case) AC Test Loads and Waveforms R1 ALL INPUT PULSES V CC 3V 90% OUTPUT 90% 10% 10% GND R2 30 pF Rise Time = 1 V/ns Fall Time = 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THEVENIN EQUIVALENT R TH OUTPUT V Parameters Value Unit R1 1350
ページ5に含まれる内容の要旨
® CY62157EV18 MoBL [11, ] 12 Switching Characteristics (Over the Operating Range) 55 ns Parameter Description Unit Min Max Read Cycle t Read Cycle Time 55 ns RC t Address to Data Valid 55 ns AA t Data Hold from Address Change 10 ns OHA t CE LOW and CE HIGH to Data Valid 55 ns ACE 1 2 t OE LOW to Data Valid 25 ns DOE [13] t OE LOW to Low-Z 5ns LZOE [13, 14] t OE HIGH to High-Z 18 ns HZOE [13] t CE LOW and CE HIGH to Low-Z 10 ns LZCE 1 2 [13, 14] t CE HIGH and CE LOW to High-Z 18 ns HZCE 1 2 t
ページ6に含まれる内容の要旨
® CY62157EV18 MoBL Switching Waveforms [17, 18] Read Cycle 1 (Address Transition Controlled) t RC RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID [18, 19] Read Cycle 2 (OE Controlled) ADDRESS t RC CE 1 t PD t HZCE CE 2 t ACE BHE/BLE t DBE t HZBE t LZBE OE t HZOE t DOE t LZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA OUT DATA VALID t LZCE t I CC PU V CC 50% 50% SUPPLY I SB CURRENT Notes: 17. The device is continuously selected. OE, CE = V , BHE and/or BLE = V , and CE = V . 1 IL IL 2 I
ページ7に含まれる内容の要旨
® CY62157EV18 MoBL Switching Waveforms (continued) [16, 20, 21] Write Cycle 1 (WE Controlled) t WC ADDRESS t SCE CE 1 CE 2 t t AW HA t t SA PWE WE t BW BHE/BLE OE t HD t SD DATA IO NOTE 22 VALID DATA t HZOE [16, 20, 21] Write Cycle 2 (CE or CE Controlled) 1 2 t WC ADDRESS t SCE CE 1 CE 2 t SA t t AW HA t PWE WE t BW BHE/BLE OE t HD t SD DATA IO NOTE 22 VALID DATA t HZOE Notes: 20. Data IO is high impedance if OE = V . IH 21. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the ou
ページ8に含まれる内容の要旨
® CY62157EV18 MoBL Switching Waveforms (continued) [21] Write Cycle 3 (WE Controlled, OE LOW) t WC ADDRESS t SCE CE 1 CE 2 t BW BHE/BLE t t AW HA t t SA PWE WE t t SD HD NOTE 22 DATA IO VALID DATA t LZWE t HZWE [21] Write Cycle 4 (BHE/BLE Controlled, OE LOW) t WC ADDRESS CE 1 CE 2 t SCE t t AW HA t BW BHE/BLE t SA t PWE WE t t SD HD DATA IO NOTE 22 VALID DATA Document #: 38-05490 Rev. *D Page 8 of 12 [+] Feedback
ページ9に含まれる内容の要旨
® CY62157EV18 MoBL Truth Table CE CE WE OE BHE BLE Inputs/Outputs Mode Power 1 2 H X X X X X High-Z Deselect/Power Down Standby (I ) SB X L X X X X High-Z Deselect/Power Down Standby (I ) SB X X X X H H High-Z Deselect/Power Down Standby (I ) SB L H H L L L Data Out (IO –IO ) Read Active (I ) 0 15 CC L H H L H L Data Out (IO –IO ); Read Active (I ) 0 7 CC High-Z (IO –IO ) 8 15 L H H L L H High-Z (IO –IO ); Read Active (I ) 0 7 CC Data Out (IO –IO ) 8 15 L H H H L H High-Z Output Disabled Active
ページ10に含まれる内容の要旨
® CY62157EV18 MoBL Package Diagrams Figure 1. 48-ball VFBGA (6 x 8 x 1 mm), 51-85150 BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 1 2346 5 65 4 3 2 1 A A B B C C D D E E F F G G H H 1.875 A A 0.75 B 6.00±0.10 3.75 B 6.00±0.10 0.15(4X) SEATING PLANE C 51-85150-*D MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. D
ページ11に含まれる内容の要旨
® CY62157EV18 MoBL Document History ® Document Title: CY62157EV18 MoBL 8-Mbit (512K x 16) Static RAM Document Number:38-05490 Orig. of REV. ECN NO. Issue Date Description of Change Change ** 202862 See ECN AJU New Data Sheet *A 291272 See ECN SYT Converted from Advance Information to Preliminary Changed V Max from 2.20 to 2.25 V CC Changed V stabilization time in footnote #7 from 100 µs to 200 µs CC Changed I from 4 to 4.5 µA CCDR Changed t from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin
ページ12に含まれる内容の要旨
® CY62157EV18 MoBL ® Document Title: CY62157EV18 MoBL 8-Mbit (512K x 16) Static RAM Document Number:38-05490 Orig. of REV. ECN NO. Issue Date Description of Change Change *D 908120 See ECN VKN Added footnote #7 related to I SB2 Added footnote #12 related AC timing parameters Document #: 38-05490 Rev. *D Page 12 of 12 [+] Feedback
