ページ1に含まれる内容の要旨
CY14E256L
256 Kbit (32K x 8) nvSRAM
Features Functional Description
■ 25 ns, 35 ns, and 45 ns access times The Cypress CY14E256L is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
■ Pin compatible with STK14C88
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
■ Hands off automatic STORE on power down with external 68
unlimited read and write cycles, while independent, nonvolatile
µF c
ページ2に含まれる内容の要旨
CY14E256L Pin Configurations Figure 1. Pin Diagram: 32-Pin SOIC/DIP Pin Definitions Pin Name Alt IO Type Description A –A Input Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM. 0 14 DQ -DQ Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation. 0 7 Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO WE W pins is written to the specific address location. Input Chip Enable Input, Active LOW.
ページ3に含まれる内容の要旨
CY14E256L having a capacitor of between 68uF and 220uF (+ 20%) rated at Device Operation 6V should be provided. The voltage on the V pin is driven to CAP 5V by a charge pump internal to the chip. A pull up is placed on The CY14E256L nvSRAM is made up of two functional compo- WE to hold it inactive during power up. nents paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM Figure 2. AutoStore Mode memory cell operates as a standard fast st
ページ4に含まれる内容の要旨
CY14E256L Figure 3. AutoStore Inhibit Mode If the CY14E256L is in a WRITE state at the end of power up RECALL, the SRAM data is corrupted. To help avoid this situation, a 10 Kohm resistor is connected either between WE and system V or between CE and system V . CC CC Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The CY14E256L software STORE cycle is initiated by executing sequential CE controlled READ cycles from six specific address
ページ5に含まれる内容の要旨
CY14E256L Figure 4. Current Versus Cycle Time (READ) Data Protection The CY14E256L protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The low voltage condition is detected when V is less than V . If the CY14E256L is in a WRITE CC SWITCH mode (both CE and WE are low) at power up after a RECALL or after a STORE, the WRITE is inhibited until a negative transition on CE or WE is detected. This protects against inadvertent w
ページ6に含まれる内容の要旨
CY14E256L manufacturing test to ensure these system routines work Best Practices consistently. nvSRAM products have been used effectively for over 15 years. ■ Power up boot firmware routines should rewrite the nvSRAM While ease of use is one of the product’s main system values, into the desired state. While the nvSRAM is shipped in a preset experience gained working with hundreds of applications has state, best practice is to again rewrite the nvSRAM into the resulted in the following sugge
ページ7に含まれる内容の要旨
CY14E256L Package Power Dissipation Maximum Ratings Capability (T = 25°C) ................................................... 1.0W A Exceeding maximum ratings may shorten the useful life of the Surface Mount Lead Soldering device. These user guidelines are not tested. Temperature (3 Seconds).......................................... +260 °C Storage Temperature ................................. –65 °C to +150 °C DC output Current (1 output at a time, 1s duration) .... 15 mA Ambient Temperature w
ページ8に含まれる内容の要旨
CY14E256L DC Electrical Characteristics [6] Over the operating range (continued)(V = 4.5V to 5.5V) CC Parameter Description Test Conditions Min Max Unit V Output LOW Voltage I = 8 mA 0.4 V OL OUT V Logic ‘0’ Voltage on HSB I = 3 mA 0.4 V BL OUT Output V Storage Capacitor Between V pin and Vss, 6V rated. 68 µF +20% nom. 54 260 uF CAP CAP Data Retention and Endurance Parameter Description Min Unit DATA Data Retention 100 Years R NV Nonvolatile STORE Operations 1,000 K C Capacitance [8] In the fol
ページ9に含まれる内容の要旨
CY14E256L AC Switching Characteristics SRAM Read Cycle Parameter 25 ns 35 ns 45 ns Description Unit Cypress Alt Min Max Min Max Min Max Parameter t t Chip Enable Access Time 25 35 45 ns ACE ELQV [9] t t t Read Cycle Time 25 35 45 ns RC AVAV, ELEH [10] t t Address Access Time 25 35 45 ns AA AVQV t t Output Enable to Data Valid 10 15 20 ns DOE GLQV [10] t t Output Hold After Address Change 5 5 5 ns OHA AXQX [11] t t Chip Enable to Output Active 5 5 5 ns LZCE ELQX [11] t t Chip Disable to Output
ページ10に含まれる内容の要旨
CY14E256L SRAM Write Cycle Parameter 25 ns 35 ns 45 ns Description Unit Cypress Alt Min Max Min Max Min Max Parameter t t Write Cycle Time 25 35 45 ns WC AVAV t t t Write Pulse Width 20 25 30 ns PWE WLWH, WLEH t t t Chip Enable To End of Write 20 25 30 ns SCE ELWH, ELEH t t t Data Setup to End of Write 10 12 15 ns SD DVWH, DVEH t t t Data Hold After End of Write 0 0 0 ns HD WHDX, EHDX t t t Address Setup to End of Write 20 25 30 ns AW AVWH, AVEH t t t Address Setup to Start of Write 0 0 0 ns SA
ページ11に含まれる内容の要旨
CY14E256L AutoStore or Power Up RECALL CY14E256L Parameter Alt Description Unit Min Max [15] t t Power up RECALL Duration 550 μs HRECALL RESTORE [16] t t STORE Cycle Duration 10 ms STORE HLHZ [16] t t t Time Allowed to Complete SRAM Cycle 1 μs DELAY HLQZ , BLQZ V Low Voltage Trigger Level 4.0 4.5 V SWITCH V Low Voltage Reset Level 3.6 V RESET t V Rise Time 150 μs VCCRISE CC [13] t Low Voltage Trigger (V ) to HSB low 300 ns VSBL SWITCH Switching Waveforms Figure 11. AutoStore/Power Up RECALL W
ページ12に含まれる内容の要旨
CY14E256L Software Controlled STORE/RECALL Cycle [19] The software controlled STORE/RECALL cycle follows. 25 ns 35 ns 45 ns Parameter Alt Description Unit Min Max Min Max Min Max [16] t t STORE/RECALL Initiation Cycle Time 25 35 45 ns RC AVAV [18, 19] t t Address Setup Time 0 0 0 ns SA AVEL [18, 19] t t Clock Pulse Width 20 25 30 ns CW ELEH [18, 19] t t Address Hold Time 20 20 20 ns HACE ELAX RECALL Duration 20 20 20 μs t RECALL Switching Waveforms [19] Figure 12. CE Controlled Software STORE
ページ13に含まれる内容の要旨
CY14E256L Hardware STORE Cycle CY14E256L Parameter Alt Description Unit Min Max [16, 20] t t t Hardware STORE High to Inhibit Off 700 ns DHSB RECOVER, HHQX t t Hardware STORE Pulse Width 15 ns PHSB HLHX t Hardware STORE Low to STORE Busy 300 ns HLBL Switching Waveforms Figure 13. Hardware STORE Cycle Note 20. t is only applicable after t is complete. DHSB STORE Document Number: 001-06968 Rev. *F Page 13 of 18 [+] Feedback
ページ14に含まれる内容の要旨
CY14E256L Part Numbering Nomenclature (Commercial and Industrial) CY 14 E 256 L- SZ 25 X C T Option: T-Tape and Reel Blank - Std. Temperature: C - Commercial (0 to 70°C) I - Industrial (-40 to 85°C) Speed: Pb-Free 25 - 25 ns 35 - 35 ns Package 45 - 45 ns SZ - 32-SOIC D - 32-CDIP Data Bus: Density: L - x8 256 - 256 Kb Voltage: E - 5.0V nvSRAM 14 - AutoStore + Software Store + Hardware Store Cypress Ordering Information Speed Operating Ordering Code Package Diagram Package Type (ns) Range 25 CY
ページ15に含まれる内容の要旨
CY14E256L Package Diagram Figure 14. 32-Pin (300 Mil) SOIC (51-85127) PIN 1 ID 16 1 MIN. DIMENSIONS IN INCHES[MM] 0.292[7.416] 0.299[7.594] MAX. 0.405[10.287] REFERENCE JEDEC MO-119 0.419[10.642] PART # 17 32 S32.3 STANDARD PKG. SZ32.3 LEAD FREE PKG. SEATING PLANE 0.810[20.574] 0.822[20.878] 0.090[2.286] 0.100[2.540] 0.004[0.101] 0.050[1.270] 0.006[0.152] 0.026[0.660] 51-85058 *A 0.021[0.533] TYP. 0.012[0.304] 0.032[0.812] 0.041[1.041] 0.004[0.101] 0.0100[0.254] 0.014[0.355] 0.020[0.508] 51-851
ページ16に含まれる内容の要旨
CY14E256L Package Diagram (continued) Figure 15. 32-Pin (300 Mil) CDIP (001-51694) 001-51694 ** Document Number: 001-06968 Rev. *F Page 16 of 18 [+] Feedback
ページ17に含まれる内容の要旨
CY14E256L Document History Page Document Title: CY14E256L 256 Kbit (32K x 8) nvSRAM Document Number: 001-06968 Submission Orig. of Rev. ECN No. Description of Change Date Change ** 427789 See ECN TUP New data sheet *A 437321 See ECN TUP Show data sheet on external Web *B 472053 See ECN TUP Updated Part Numbering Nomenclature and Ordering Information *C 503290 See ECN PCI Changed from “Advance” to “Preliminary” Changed the term “Unlimited” to “Infinite” Changed I value from 10mA to 15mA CC3 Re
ページ18に含まれる内容の要旨
CY14E256L Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales Products PSoC Solutions PSoC psoc.cypress.com General psoc.cypress.com/solutions Clocks & Buffers clocks.cypress.com Low Power/Low Voltage psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog psoc.cypress.com/pr
