ページ1に含まれる内容の要旨
®
CY62148ESL MoBL
4-Mbit (512K x 8) Static RAM
Features Functional Description
■ Very high speed: 55 ns The CY62148ESL is a high performance CMOS static RAM
organized as 512K words by 8 bits. This device features
■ Wide voltage range: 2.2V to 3.6V and 4.5V to 5.5V
advanced circuit design to provide ultra low active current. This
®
is ideal for providing More Battery Life™ (MoBL ) in portable
■ Ultra low standby power
applications such as cellular telephones. The device also has an
❐ Typical s
ページ2に含まれる内容の要旨
® CY62148ESL MoBL Pin Configuration Figure 1. 32-Pin STSOP (Top View) A 25 24 OE 11 A A 26 23 9 10 A 27 22 CE 8 1 A 28 21 IO 13 7 WE 29 20 IO 6 A 30 19 IO 5 17 STSOP IO A 31 18 15 4 Top View V 32 17 IO CC 3 A 1 16 GND 18 (not to scale) IO A 2 15 16 2 A 3 14 IO 14 1 A IO 4 13 12 0 A A 5 12 7 0 A A 6 11 6 1 A A 7 10 5 2 A A 8 9 4 3 Product Portfolio Power Dissipation Operating I , (mA) CC Speed Standby, I [1] SB2 Product Range V Range (V) CC (ns) (μA) f = 1 MHz f = f max [2] [2] [2] Typ Max Ty
ページ3に含まれる内容の要旨
® CY62148ESL MoBL Output Current into Outputs (LOW)............................. 20 mA Maximum Ratings Static Discharge Voltage.......................................... > 2001V Exceeding maximum ratings may impair the useful life of the (MIL-STD-883, Method 3015) device. These user guidelines are not tested. Latch Up Current .................................................... > 200 mA Storage Temperature.................................. –65°C to +150°C Operating Range Ambient Temperature with
ページ4に含まれる内容の要旨
® CY62148ESL MoBL Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description Test Conditions Max Unit C Input Capacitance T = 25°C, f = 1 MHz, 10 pF IN A V = V CC CC(typ) C Output Capacitance 10 pF OUT Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description Test Conditions STSOP Unit Θ Thermal Resistance Still Air, soldered on a 3 x 4.5 inch, two layer pr
ページ5に含まれる内容の要旨
® CY62148ESL MoBL Data Retention Characteristics Over the Operating Range [2] Parameter Description Conditions Min Typ Max Unit V V for Data Retention 1.5 V DR CC I Data Retention Current CE > V – 0.2V, V = 1.5V 1 7 μA CCDR CC CC V > V – 0.2V or V < 0.2V IN CC IN [7] t Chip Deselect to Data 0ns CDR Retention Time [8] t Operation Recovery Time t ns R RC Data Retention Waveform DATA RETENTION MODE V V V CC(min) V > 1.5V CC(min) DR CC t t CDR R CE Notes 7. Tested initially and after any design or
ページ6に含まれる内容の要旨
® CY62148ESL MoBL Switching Characteristics [9] Over the Operating Range 55 ns Parameter Description Unit Min Max Read Cycle t Read Cycle Time 55 ns RC t Address to Data Valid 55 ns AA t Data Hold from Address Change 10 ns OHA t CE LOW to Data Valid 55 ns ACE t OE LOW to Data Valid 25 ns DOE [10] t OE LOW to Low Z 5ns LZOE [10, 11] t OE HIGH to High Z 20 ns HZOE [10] t CE LOW to Low Z 10 ns LZCE [10, 11] t CE HIGH to High Z 20 ns HZCE t CE LOW to Power Up 0 ns PU t CE HIGH to Power Up 55 ns PD
ページ7に含まれる内容の要旨
® CY62148ESL MoBL Switching Waveforms [13, 14] Figure 3. Read Cycle No. 1 (Address Transition Controlled) tRC RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID [14, 15] Figure 4. Read Cycle No. 2 (OE Controlled) ADDRESS t RC CE t ACE OE t HZOE t DOE t HZCE t LZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID DATA OUT t LZCE t PD t I V PU CC CC SUPPLY 50% 50% CURRENT I SB [16, 17] Figure 5. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) t WC ADDRESS t SCE CE t t AW HA t t
ページ8に含まれる内容の要旨
® CY62148ESL MoBL Switching Waveforms (continued) [16, 17] Figure 6. Write Cycle No. 2 (CE Controlled) t WC ADDRESS t SCE CE t SA t t AW HA t PWE WE t t SD HD DATA IO DATA VALID [17] Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE t t SD HD NOTE 18 DATA VALID DATA IO t t LZWE HZWE Truth Table CE WE OE Inputs/Outputs Mode Power H X X High Z Deselect/Power Down Standby (I ) SB L H L Data Out Read Active (I ) CC L H H High Z Output Disabled Act
ページ9に含まれる内容の要旨
® CY62148ESL MoBL Ordering Information Speed Package Operating Ordering Code Package Type (ns) Diagram Range 55 CY62148ESL-55ZAXI 51-85094 32-Pin STSOP (Pb-Free) Industrial Package Diagram Figure 8. 32-Pin Shrunk Thin Small Outline Package (8 x 13.4 mm), 51-85094 51-85094-*D Document #: 001-50045 Rev. ** Page 9 of 10 [+] Feedback
ページ10に含まれる内容の要旨
® CY62148ESL MoBL Document History Page ® Document Title: CY62148ESL MoBL 4-Mbit (512K x 8) Static RAM Document Number: 001-50045 Rev. ECN No. Orig. of Submission Description of Change Change Date ** 2612938 VKN/PYRS 01/21/09 New data sheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.
