ページ1に含まれる内容の要旨
CY62146DV30
4-Mbit (256K x 16) Static RAM
an automatic power-down feature that significantly reduces
Features
power consumption. The device can also be put into standby
• Very high speed: 45 ns mode reducing power consumption by more than 99% when
deselected (CE HIGH). The input/output pins (I/O through
0
• Wide voltage range: 2.20V–3.60V
I/O ) are placed in a high-impedance state when: deselected
15
• Pin-compatible with CY62146CV30
(CE HIGH), outputs are disabled (OE HIGH), both Byte High
En
ページ2に含まれる内容の要旨
CY62146DV30 [2, 3, 4] Pin Configuration VFBGA (Top View) 44 TSOP II (Top View) 1 2 3 4 5 6 44 1 A A 4 5 A A OE A NC A 2 43 A BLE 0 1 2 A 3 6 3 42 A A 2 7 4 41 A OE 1 A A I/O BHE CE I/O B 4 8 3 0 40 A 5 BHE 0 39 6 CE BLE 38 I/O A A C 7 I/O I/O I/O I/O I/O 0 15 9 10 5 6 1 2 37 I/O 8 I/O 1 14 36 I/O 9 I/O 2 13 Vcc V A I/O A I/O SS 7 D 35 11 17 3 I/O 10 I/O 3 12 34 V V 11 CC SS 33 Vss V 12 V V DNU A SS CC I/O I/O E CC 16 12 4 I/O 13 32 I/O 4 11 31 I/O I/O 5 14 10 A A F I/O I/O I/O I/O I/O 30 15
ページ3に含まれる内容の要旨
CY62146DV30 [6, 7] DC Input Voltage .....................–0.3V to V + 0.3V Maximum Ratings CC(MAX) Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guide- Static Discharge Voltage........................................... >2001V lines, not tested.) (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch-up Current...................................................... >2
ページ4に含まれる内容の要旨
CY62146DV30 [9] Capacitance (for all packages) Parameter Description Test Conditions Max. Unit C Input Capacitance T = 25°C, f = 1 MHz, 10 pF IN A V = V CC CC(typ) C Output Capacitance 10 pF OUT [9] Thermal Resistance Parameter Description Test Conditions BGA TSOP II Unit Θ Thermal Resistance Still Air, soldered on a 3 × 4.5 inch, four-layer 72 75.13 °C/W JA (Junction to Ambient) printed circuit board Θ Thermal Resistance 8.86 8.95 °C/W JC (Junction to Case) [10] AC Test Loads and Waveforms R1
ページ5に含まれる内容の要旨
CY62146DV30 [12] Switching Characteristics Over the Operating Range [10] 45 ns 55 ns 70 ns Parameter Description Min. Max. Min. Max. Min. Max. Unit Read Cycle t Read Cycle Time 45 55 70 ns RC t Address to Data Valid 45 55 70 ns AA t Data Hold from Address Change 10 10 10 ns OHA t CE LOW to Data Valid 45 55 70 ns ACE t OE LOW to Data Valid 25 25 35 ns DOE [13] t OE LOW to LOW Z 55 5 ns LZOE [13, 14] t OE HIGH to High Z 15 20 25 ns HZOE [13] t CE LOW to Low Z 10 10 10 ns LZCE [13, 14] t CE HIGH
ページ6に含まれる内容の要旨
CY62146DV30 Switching Waveforms [16, 17] Read Cycle 1 (Address Transition Controlled) t RC ADDRESS t AA t OHA DATA OUT PREVIOUS DATA VALID DATA VALID [17, 18] Read Cycle No. 2 (OE Controlled) ADDRESS t RC CE t PD t t HZCE ACE OE t HZOE t DOE BHE/BLE t LZOE t HZBE t DBE t LZBE HIGH IMPEDANCE HIGH IMPEDANCE DATA OUT DATA VALID t LZCE t PU V I CC CC SUPPLY 50% 50% CURRENT I SB Notes: 16. The device is continuously selected. OE, CE = V , BHE and/or BLE = V . IL IL 17. WE is HIGH for read cycle.
ページ7に含まれる内容の要旨
CY62146DV30 Switching Waveforms (continued) [15, 19, 20] Write Cycle No. 1 (WE Controlled) t WC ADDRESS t SCE CE t t AW HA t t SA PWE WE t BW BHE/BLE OE t SD t HD DATA I/O NOTE 21 DATA IN t HZOE [15, 19, 20] Write Cycle No. 2 (CE Controlled) t WC ADDRESS t SCE CE t SA t t AW HA t PWE WE t BW BHE/BLE OE t SD t HD DATA I/O DATA IN NOTE 21 t HZOE Notes: 19. Data I/O is high impedance if OE = V . IH 20. If CE goes HIGH simultaneously with WE = V , the output remains in a high-impedance state. I
ページ8に含まれる内容の要旨
CY62146DV30 Switching Waveforms (continued) [20] Write Cycle No. 3 (WE Controlled, OE LOW) t WC ADDRESS t SCE CE t BW BHE/BLE t t AW HA t t SA PWE WE t HD t SD NOTE 21 DATAI/O DATA IN t HZWE t LZWE [20] Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) t WC ADDRESS CE t SCE t t AW HA t BW BHE/BLE t SA t PWE WE t HZWE t t HD SD DATA I/O DATA NOTE 21 IN t LZWE Document #: 38-05339 Rev. *A Page 8 of 11 [+] Feedback
ページ9に含まれる内容の要旨
CY62146DV30 Truth Table CE WE OE BHE BLE Inputs/Outputs Mode Power H X X X X High Z Deselect/Power-Down Standby (I ) SB L X X H H High Z Output Disabled Active (I ) CC L H L L L Data Out (I/O –I/O ) Read Active (I ) O 15 CC L H L H L Data Out (I/O –I/O ); Read Active (I ) O 7 CC I/O –I/O in High Z 8 15 L H L L H Data Out (I/O –I/O ); Read Active (I ) 8 15 CC I/O –I/O in High Z 0 7 L H H L L High Z Output Disabled Active (I ) CC L H H H L High Z Output Disabled Active (I ) CC L H H L H High Z
ページ10に含まれる内容の要旨
CY62146DV30 Package Diagram 48-Lead VFBGA (6 x 8 x 1 mm) BV48A 51-85150-*B 44-Pin TSOP II ZS44 51-85087-*A MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05339 Rev. *A Page 10 of 11 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corpor
ページ11に含まれる内容の要旨
CY62146DV30 Document History Page ® Document Title:CY62146DV30 MoBL 4-Mbit (256K x 16) Static RAM Document Number: 38-05339 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 213251 See ECN AJU New Data Sheet *A 316039 See ECN PCI Added 45-ns Speed Bin in AC, DC and Ordering Information tables Added Footnote #10 on page #4 Added Pb-free package ordering information on page # 9 Changed 44-lead TSOP-II package name on page 10 from Z44 to ZS44 Standardized Icc values across ‘L’ and
