Cypress CY14B104Nの取扱説明書

ページ1に含まれる内容の要旨

CY14B104L, CY14B104N
4 Mbit (512K x 8/256K x 16) nvSRAM
Features Functional Description
■ 20 ns, 25 ns, and 45 ns Access Times The Cypress CY14B104L/CY14B104N is a fast static RAM, with
a nonvolatile element in each memory cell. The memory is
■ Internally organized as 512K x 8 (CY14B104L) or 256K x 16
organized as 512K bytes of 8 bits each or 256K words of 16 bits
(CY14B104N)
each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
■ Hands

ページ2に含まれる内容の要旨

CY14B104L, CY14B104N Pinouts Figure 1. Pin Diagram - 48 FBGA 48-FBGA 48-FBGA (x8) (x16) Top View Top View (not to scale) (not to scale) 1 2 4 5 3 6 1 2 4 3 5 6 A A A OE NC A A A BLE 0 2 A NC OE NC 1 0 1 2 A DQ A A NC 8 BHE CE DQ B A A 3 4 NC CE NC B 0 3 4 C DQ A A DQ DQ A A C DQ DQ NC NC DQ 9 5 6 1 2 5 6 10 0 4 V A V A A DQ V A V SS DQ 7 CC D SS DQ 7 DQ CC D 17 3 17 5 11 1 V A V E V A V CC DQ V DQ SS CC DQ V DQ SS E CAP 16 16 12 4 2 CAP 6 A A F A A F DQ DQ DQ DQ NC DQ 13 14 DQ 14 15 NC 14 15

ページ3に含まれる内容の要旨

CY14B104L, CY14B104N Pinouts (continued) Figure 3. Pin Diagram - 54 Pin TSOP II (x16) NC 54 HSB 1 [5] [4] NC 53 NC 2 A 52 A 0 3 17 A 51 A 1 4 16 A 50 A 2 5 15 49 A 3 6 OE 48 A BHE 4 7 CE 47 8 BLE DQ 46 DQ 0 9 15 DQ 10 45 DQ 1 14 54 - TSOP II DQ 11 44 DQ 2 13 (x16) DQ 43 DQ 12 3 12 V 42 CC V 13 Top View SS V 41 SS V 14 CC (not to scale) 40 DQ DQ 4 15 11 DQ 39 DQ 5 16 10 38 DQ DQ 17 6 9 37 DQ DQ 18 7 8 36 WE V 19 CAP 35 A A 5 20 14 34 A A 6 21 13 33 A A 22 12 7 32 A A 23 11 8 31 A 24 A 10 9 30 N

ページ4に含まれる内容の要旨

CY14B104L, CY14B104N Figure 4 shows the proper connection of the storage capacitor Device Operation (V ) for automatic store operation. Refer to DC Electrical CAP The CY14B104L/CY14B104N nvSRAM is made up of two Characteristics on page 7 for the size of V . The voltage on CAP functional components paired in the same physical cell. They are the V pin is driven to V by a regulator on the chip. A pull CAP CC an SRAM memory cell and a nonvolatile QuantumTrap cell. The up should be placed on WE to h

ページ5に含まれる内容の要旨

CY14B104L, CY14B104N The software sequence may be clocked with CE controlled reads Hardware RECALL (Power Up) or OE controlled reads. After the sixth address in the sequence During power up or after any low power condition is entered, the STORE cycle commences and the chip is (V

ページ6に含まれる内容の要旨

CY14B104L, CY14B104N Table 1. Mode Selection (continued) [7] [3] A - A Mode IO Power CE WE OE, BHE, BLE 15 0 [8, 9] L H L 0x4E38 Read SRAM Output Data Active 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x4B46 AutoStore Enable Output Data [8, 9] L H L 0x4E38 Read SRAM Output Data Active I CC2 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8FC0 Nonvolatil

ページ7に含まれる内容の要旨

CY14B104L, CY14B104N Transient Voltage (<20 ns) on Maximum Ratings Any Pin to Ground Potential .................. –2.0V to V + 2.0V CC Exceeding maximum ratings may impair the useful life of the Package Power Dissipation device. These user guidelines are not tested. Capability (T = 25°C) ................................................... 1.0W A Storage Temperature ................................. –65°C to +150°C Surface Mount Pb Soldering Temperature (3 Seconds)..............................

ページ8に含まれる内容の要旨

CY14B104L, CY14B104N Data Retention and Endurance Parameter Description Min Unit DATA Data Retention 20 Years R NV Nonvolatile STORE Operations 200 K C Capacitance [13] In the following table, the capacitance parameters are listed. Parameter Description Test Conditions Max Unit C Input Capacitance T = 25°C, f = 1 MHz, 7pF IN A V = 0 to 3.0V CC C Output Capacitance 7 pF OUT Thermal Resistance [13] In the following table, the thermal resistance parameters are listed. Parameter Description Test Co

ページ9に含まれる内容の要旨

CY14B104L, CY14B104N AC Switching Characteristics Parameters 20 ns 25 ns 45 ns Description Unit Cypress Alt Min Max Min Max Min Max Parameters Parameters SRAM Read Cycle t t Chip Enable Access Time 20 25 45 ns ACE ACS [14] t t Read Cycle Time 20 25 45 ns RC RC [15] t t Address Access Time 20 25 45 ns AA AA t t Output Enable to Data Valid 10 12 20 ns DOE OE [15] t t Output Hold After Address Change 3 3 3 ns OHA OH [16] t t Chip Enable to Output Active 3 3 3 ns LZCE LZ [16] t t Chip Disable to Ou

ページ10に含まれる内容の要旨

CY14B104L, CY14B104N [3, 14, 18] Figure 7. SRAM Read Cycle #2: CE and OE Controlled [3, 17, 18, 19] Figure 8. SRAM Write Cycle #1: WE Controlled Notes 19. CE or WE must be >V during address transitions. IH Document #: 001-07102 Rev. *L Page 10 of 25 [+] Feedback

ページ11に含まれる内容の要旨

CY14B104L, CY14B104N [3, 17, 18, 19] Figure 9. SRAM Write Cycle #2: CE Controlled t WC Address Valid Address t t t SA SCE HA CE t BW BHE, BLE t PWE WE t t HD SD Data Input Input Data Valid High Impedance Data Output [3, 17, 18, 19] Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled Document #: 001-07102 Rev. *L Page 11 of 25 [+] Feedback

ページ12に含まれる内容の要旨

CY14B104L, CY14B104N AutoStore/Power Up RECALL CY14B104L/CY14B104N Parameters Description Unit Min Max [20] t Power Up RECALL Duration 20 ms HRECALL [21] t STORE Cycle Duration 8 ms STORE [22] t Time Allowed to Complete SRAM Cycle 1 70 μs DELAY V Low Voltage Trigger Level 2.65 V SWITCH t VCC Rise Time 150 μs VCCRISE [13] V HSB Output Driver Disable Voltage 1.9 V HDIS t HSB High Active Time 500 ns HHHD t HSB Hold Time after Power-Up Recall Start 70 μs PURHH t HSB To Output Active Time 5 μs LZH

ページ13に含まれる内容の要旨

CY14B104L, CY14B104N Software Controlled STORE/RECALL Cycle [25, 26] In the following table, the software controlled STORE/RECALL cycle parameters are listed. 20 ns 25 ns 45 ns Parameters Description Unit Min Max Min Max Min Max t STORE/RECALL Initiation Cycle Time 20 25 45 ns RC t Address Setup Time 0 0 0 ns SA t Clock Pulse Width 15 20 30 ns CW t Address Hold Time 0 0 0 ns HA t RECALL Duration 200 200 200 μs RECALL [27, 28] t Soft Sequence Processing Time 100 100 100 μs SS Switching Waveforms

ページ14に含まれる内容の要旨

CY14B104L, CY14B104N Hardware STORE Cycle CY14B104L/CY14B104N Parameters Description Unit Min Max t Hardware STORE Pulse Width 15 ns PHSB t Hardware STORE LOW to STORE Busy 500 ns HLBL Switching Waveforms [21] Figure 14. Hardware STORE Cycle [27, 28] Figure 15. Soft Sequence Processing Notes 27. This is the amount of time it takes to take action on a soft sequence command. V power must remain HIGH to effectively register comma

ページ15に含まれる内容の要旨

CY14B104L, CY14B104N Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations. For x8 Configuration [2] CE WE OE Inputs/Outputs Mode Power H X X High Z Deselect/Power down Standby L H L Data Out (DQ –DQ ); Read Active 0 7 L H H High Z Output Disabled Active L L X Data in (DQ –DQ ); Write Active 0 7 For x16 Configuration [2] CE WE OE BHE BLE Inputs/Outputs Mode Power H X X X X High-Z Deselect/Power down Standby L X X H H High-Z Output Disabled Active L H L L L Data Out (DQ

ページ16に含まれる内容の要旨

CY14B104L, CY14B104N Ordering Information Speed Package Operating Ordering Code Package Type (ns) Diagram Range 20 CY14B104L-ZS20XCT 51-85087 44-pin TSOP II Commercial CY14B104L-ZS20XIT 51-85087 44-pin TSOP II Industrial CY14B104L-ZS20XI 51-85087 44-pin TSOP II CY14B104L-BA20XCT 51-85128 48-ball FBGA Commercial CY14B104L-BA20XIT 51-85128 48-ball FBGA Industrial CY14B104L-BA20XI 51-85128 48-ball FBGA CY14B104L-ZSP20XCT 51-85160 54-pin TSOP II Commercial CY14B104L-ZSP20XIT 51-85160 54-pin TSOP II

ページ17に含まれる内容の要旨

CY14B104L, CY14B104N Ordering Information (continued) Speed Package Operating Ordering Code Package Type (ns) Diagram Range 45 CY14B104L-ZS45XCT 51-85087 44-pin TSOP II Commercial CY14B104L-ZS45XIT 51-85087 44-pin TSOP II Industrial CY14B104L-ZS45XI 51-85087 44-pin TSOP II CY14B104L-BA45XCT 51-85128 48-ball FBGA Commercial CY14B104L-BA45XIT 51-85128 48-ball FBGA Industrial CY14B104L-BA45XI 51-85128 48-ball FBGA CY14B104L-ZSP45XCT 51-85160 54-pin TSOP II Commercial CY14B104L-ZSP45XIT 51-85160 54

ページ18に含まれる内容の要旨

CY14B104L, CY14B104N Part Numbering Nomenclature CY 14 B 104 L - ZS P 20 X C T Option: T - Tape & Reel Blank - Std. Temperature: C - Commercial (0 to 70°C) Speed: I - Industrial (–40 to 85°C) Pb-Free 20 - 20 ns 25 - 25 ns P - 54 Pin Package: 45 - 45 ns Blank - 44 Pin BA - 48 FBGA ZS - TSOP II Data Bus: L - x8 N - x16 Density: 104 - 4 Mb Voltage: B - 3.0V NVSRAM 14 - Auto Store + Software Store + Hardware Store Cypress Document #: 001-07102 Rev. *L Page 18 of 25 [+] Feedback

ページ19に含まれる内容の要旨

CY14B104L, CY14B104N Package Diagrams Figure 16. 44-Pin TSOP II (51-85087) DIMENSION IN MM (INCH) MAX MIN. PIN 1 I.D. 22 1 R O E K A X S G 23 44 EJECTOR PIN TOP VIEW BOTTOM VIEW 10.262 (0.404) 0.400(0.016) 0.800 BSC 10.058 (0.396) 0.300 (0.012) BASE PLANE (0.0315) 0.210 (0.0083) 0°-5° 0.120 (0.0047) 0.10 (.004) 18.517 (0.729) 0.597 (0.0235) 18.313 (0.721) 0.406 (0.0160) SEATING PLANE 51-85087-*A Document #: 001-07102 Rev. *L Page 19 of 25 [+] Feedback 1.194 (0.047) 0.991 (0.039) 0.150 (0.005

ページ20に含まれる内容の要旨

CY14B104L, CY14B104N Package Diagrams (continued) Figure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128) BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 1 2346 5 65 4 3 2 1 A A B B C C D D E E F F G G H H 1.875 A A 0.75 B 6.00±0.10 3.75 B 6.00±0.10 0.15(4X) SEATING PLANE C 51-85128-*D Document #: 001-07102 Rev. *L Page 20 of 25 [+] Feedback 0.25 C 10.00±0.10 0.36 0.53±0.05 0.21±0.05 1.20 MAX 0.15 C 10.00±0.10 5.25 0.75 2.625