ページ1に含まれる内容の要旨
CY14B101L
1 Mbit (128K x 8) nvSRAM
Features Functional Description
■ 25 ns, 35 ns, and 45 ns access times The Cypress CY14B101L is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
■ Pin compatible with STK14CA8
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
■ Hands off automatic STORE on power down with only a small
unlimited read and write cycles, while independent, nonvolatile
capa
ページ2に含まれる内容の要旨
CY14B101L Pinouts Figure 1. Pin Diagram - 32-Pin SOIC and 48-Pin SSOP V 1 V CAP 48 CC A 2 VCAP 1 32 V 47 A CC 16 15 3 A 46 HSB 14 A16 2 31 A 15 A 4 12 45 WE A14 3 30 HSB A 5 A 44 7 13 A 6 43 6 A 8 A 4 29 WE 12 A 7 42 A 5 9 A 5 28 A 7 13 NC 8 41 NC A 9 40 A 4 11 A 6 27 6 A8 Top View 10 NC 39 NC A 7 26 11 (not to scale) 5 A9 NC 38 NC 12 NC NC 37 A 8 4 25 A11 V 13 SS 36 V SS 14 A3 9 24 OE NC 35 NC NC 15 34 NC A2 10 23 A 10 DQ0 16 DQ6 33 A 11 22 CE 17 1 A 3 32 OE 18 A A 31 2 10 A 12 21 DQ 0 7 A 19
ページ3に含まれる内容の要旨
CY14B101L Figure 2 shows the proper connection of the storage capacitor Device Operation (V ) for automatic store operation. Refer to the DC Electrical CAP Characteristics on page 7 for the size of V . The voltage on The CY14B101L nvSRAM is made up of two functional compo- CAP the V pin is driven to 5V by a charge pump internal to the chip. nents paired in the same physical cell. These are an SRAM CAP A pull up is placed on WE to hold it inactive during power up. memory cell and a nonvolatile Q
ページ4に含まれる内容の要旨
CY14B101L Hardware RECALL (Power Up) Data Protection During power up or after any low power condition (V < The CY14B101L protects data from corruption during low CC V ), an internal RECALL request is latched. When V voltage conditions by inhibiting all externally initiated STORE SWITCH CC once again exceeds the sense voltage of V , a RECALL and WRITE operations. The low voltage condition is detected SWITCH cycle is automatically initiated and takes t to complete. when V is less than V . HRECALL
ページ5に含まれる内容の要旨
CY14B101L Preventing Store Best Practices Disable the AutoStore function by initiating an AutoStore Disable nvSRAM products have been used effectively for over 15 years. sequence. A sequence of READ operations is performed in a While ease of use is one of the product’s main system values, manner similar to the software STORE initiation. To initiate the experience gained working with hundreds of applications has AutoStore Disable sequence, perform the following sequence of resulted in the follow
ページ6に含まれる内容の要旨
CY14B101L . Table 1. Hardware Mode Selection A – A Mode IO Power CE WE OE 15 0 H X X X Not Selected Output High Z Standby [3] L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active [1, 2, 3] LH L 0x4E38 Read SRAM Output Data Active 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8B45 AutoStore Disable Output Data [1, 2, 3] LH L 0x4E38 Read SRAM Output Data Active 0xB1C7 Read SRAM Output Data 0x83E0 Read SR
ページ7に含まれる内容の要旨
CY14B101L Package Power Dissipation Maximum Ratings Capability (T = 25°C) ................................................... 1.0W A Exceeding maximum ratings may shorten the useful life of the Surface Mount Lead Soldering device. These user guidelines are not tested. Temperature (3 Seconds).......................................... +260°C Storage Temperature ................................. –65°C to +150°C DC output Current (1 output at a time, 1s duration) .... 15 mA Ambient Temperature with
ページ8に含まれる内容の要旨
CY14B101L Data Retention and Endurance Parameter Description Min Unit DATA Data Retention at 55°C20Years R NV Nonvolatile STORE Operations 200 K C Capacitance [6] In the following table, the capacitance parameters are listed. Parameter Description Test Conditions Max Unit C Input Capacitance T = 25°C, f = 1 MHz, 7pF IN A V = 0 to 3.0V CC C Output Capacitance 7 pF OUT Thermal Resistance [6] In the following table, the thermal resistance parameters are listed. Parameter Description Test Conditions
ページ9に含まれる内容の要旨
CY14B101L AC Switching Characteristics SRAM Read Cycle Parameter 25 ns 35 ns 45 ns Description Unit Cypress Alt Min Max Min Max Min Max Parameter t t Chip Enable Access Time 25 35 45 ns ACE ELQV [7] t t t Read Cycle Time 25 35 45 ns RC AVAV, ELEH [8] t t Address Access Time 25 35 45 ns AA AVQV t t Output Enable to Data Valid 12 15 20 ns DOE GLQV [8] t t Output Hold After Address Change 3 3 3 ns OHA AXQX [9] t t Chip Enable to Output Active 3 3 3 ns LZCE ELQX [9] t t Chip Disable to Output Inac
ページ10に含まれる内容の要旨
CY14B101L SRAM Write Cycle Parameter 25 ns 35 ns 45 ns Description Unit Cypress Alt Min Max Min Max Min Max Parameter t t Write Cycle Time 25 35 45 ns WC AVAV t t t Write Pulse Width 20 25 30 ns PWE WLWH, WLEH t t t Chip Enable To End of Write 20 25 30 ns SCE ELWH, ELEH t t t Data Setup to End of Write 10 12 15 ns SD DVWH, DVEH t t t Data Hold After End of Write 0 0 0 ns HD WHDX, EHDX t t t Address Setup to End of Write 20 25 30 ns AW AVWH, AVEH t t t Address Setup to Start of Write 0 0 0 ns SA
ページ11に含まれる内容の要旨
CY14B101L AutoStore or Power Up RECALL CY14B101L Parameter Alt Description Unit Min Max [13] t t Power up RECALL Duration 20 ms HRECALL RESTORE [14, 15] t t STORE Cycle Duration 12.5 ms STORE HLHZ V Low Voltage Trigger Level 2.65 V SWITCH t V Rise Time 150 μs VCCRISE CC Switching Waveforms Figure 9. AutoStore/Power Up RECALL STORE occurs only No STORE occurs without atleast one if a SRAM write has happened SRAM write V CC V SWITCH tVCCRISE AutoStore t t STORE STORE POWER-UP RECALL t t HRECA
ページ12に含まれる内容の要旨
CY14B101L Software Controlled STORE/RECALL Cycle [16, 17] The software controlled STORE/RECALL cycle follows. 25 ns 35 ns 45 ns Parameter Alt Description Unit Min Max Min Max Min Max [17] t t STORE/RECALL Initiation Cycle Time 25 35 45 ns RC AVAV t t Address Setup Time 0 0 0 ns SA AVEL t t Clock Pulse Width 20 25 30 ns CW ELEH t t t Address Hold Time 1 1 1 ns HA GHAX, ELAX RECALL Duration 120 120 120 μs t RECALL Switching Waveforms [17] Figure 10. CE Controlled Software STORE/RECALL Cycle t
ページ13に含まれる内容の要旨
CY14B101L Hardware STORE Cycle CY14B101L Parameter Alt Description Unit Min Max t t Hardware STORE Pulse Width 15 ns PHSB HLHX [18] t t t Time Allowed to Complete SRAM Cycle 1 70 μs DELAY HLQZ , BLQZ [19, 20] t Soft Sequence Processing Time 70 us ss Switching Waveforms Figure 12. Hardware STORE Cycle [19, 20] Figure 13. Soft Sequence Processing Notes 18. On a hardware STORE initiation, SRAM operation continues to be enabled for time t to allow read and write
ページ14に含まれる内容の要旨
CY14B101L Part Numbering Nomenclature CY 14 B 101 L - SZ 25 X C T Option T - Tape and Reel Blank - Std. Temperature C - Commercial (0 to 70°C) I - Industrial (–40 to 85°C) Pb-Free Speed 25 - 25 ns Package 35 - 35 ns SZ - 32 SOIC 45 - 45 ns SP - 48 SSOP Data Bus L - x8 Density 101 - 1 Mb Voltage B - 3.0V NVSRAM 14 - AutoStore + Software Store + Hardware Store Cypress Ordering Information Speed Operating Ordering Code Package Diagram Package Type (ns) Range 25 CY14B101L-SZ25XCT 51-85127 32-pin S
ページ15に含まれる内容の要旨
CY14B101L Ordering Information Speed Operating Ordering Code Package Diagram Package Type (ns) Range 45 CY14B101L-SZ45XCT 51-85127 32-pin SOIC Commercial CY14B101L-SZ45XC 51-85127 32-pin SOIC CY14B101L-SP45XCT 51-85061 48-pin SSOP CY14B101L-SP45XC 51-85061 48-pin SSOP CY14B101L-SZ45XIT 51-85127 32-pin SOIC Industrial CY14B101L-SZ45XI 51-85127 32-pin SOIC CY14B101L-SP45XIT 51-85061 48-pin SSOP CY14B101L-SP45XI 51-85061 48-pin SSOP All parts are Pb-free. The above table contains Final informati
ページ16に含まれる内容の要旨
CY14B101L Package Diagrams (continued) Figure 15. 48-Pin Shrunk Small Outline Package (51-85061) 51-85061-*C Document Number: 001-06400 Rev. *I Page 16 of 18 [+] Feedback
ページ17に含まれる内容の要旨
CY14B101L Document History Page Document Title: CY14B101L 1 Mbit (128K x 8) nvSRAM Document Number: 001-06400 Submission Orig. of Rev. ECN No. Description of Change Date Change ** 425138 TUP New data sheet *A 437321 TUP Show data sheet on External Web *B 471966 TUP Changed I from 5 mA to 10 mA CC3 Changed ISB from 2 mA to 3 mA Changed V from 2.2V to 2.0V IH(min) Changed t from 40 μs to 50 μs RECALL Changed Endurance from 1 million Cycles to 500K Cycles Changed Data Retention from 100 years to
ページ18に含まれる内容の要旨
CY14B101L Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales Products PSoC Solutions PSoC psoc.cypress.com General psoc.cypress.com/solutions Clocks & Buffers clocks.cypress.com Low Power/Low Voltage psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog psoc.cypress.com/pr
