ページ1に含まれる内容の要旨
Features
®
• High-performance, Low-power AVR 8-bit Microcontroller
� Advanced RISC Architecture
– 131 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-chip 2-cycle Multiplier
� High Endurance Non-volatile Memory segments
– 32K Bytes of In-System Self-programmable Flash program memory
– 1K Bytes EEPROM
8-bit
– 2K Bytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/ 100,000
ページ2に含まれる内容の要旨
1. Pin Configurations 1.1 Pinout - PDIP/TQFP/VQFN/QFN/MLF Figure 1-1. Pinout PDIP (PCINT8/XCK0/T0) PB0 PA0 (ADC0/PCINT0) (PCINT9/CLKO/T1) PB1 PA1 (ADC1/PCINT1) (PCINT10/INT2/AIN0) PB2 PA2 (ADC2/PCINT2) (PCINT11/OC0A/AIN1) PB3 PA3 (ADC3/PCINT3) (PCINT12/OC0B/SS) PB4 PA4 (ADC4/PCINT4) (PCINT13/MOSI) PB5 PA5 (ADC5/PCINT5) (PCINT14/MISO) PB6 PA6 (ADC6/PCINT6) (PCINT15/SCK) PB7 PA7 (ADC7/PCINT7) RESET AREF VCC GND GND AVCC XTAL2 PC7 (TOSC2/PCINT23) XTAL1 PC6 (TOSC1/PCINT22) (PCINT2
ページ3に含まれる内容の要旨
A24 B20 A23 B19 A22 B18 A21 B17 A20 B16 A19 A19 B16 A20 B17 A21 B18 A22 B19 A23 B20 A24 ATmega324PA 1.2 Pinout - DRQFN Figure 1-2. DRQFN - Pinout Top view Bottom view A1 A18 A18 A1 B1 B15 B15 B1 A2 A17 A17 A2 B2 B14 B14 B2 A3 A16 A16 A3 B3 B13 B13 B3 A4 A15 A15 A4 B4 B12 B12 B4 A5 A14 A14 A5 B5 B11 B11 B5 A6 A13 A13 A6 Table 1-1
ページ4に含まれる内容の要旨
1.3 Pinout - VFBGA Figure 1-3. VFBGA - Pinout Top view Bottom view 1 234567 765432 1 A A B B C C D D E E F F G G Table 1-2. BGA - Pinout 123 4567 A GND PB4 PB2 GND VCC PA2 GND B PB6 PB5 PB3 PB0 PA0 PA3 PA5 C VCC RESET PB7 PB1 PA1 PA6 AREF D GND XTAL2 PD0 GND PA4 PA7 GND E XTAL1 PD1 PD5 PD7 PC5 PC7 AVCC F PD2 PD3 PD6 PC0 PC2 PC4 PC6 G GND PD4 VCC GND PC1 PC3 GND 4 ATmega324PA 8152AS–AVR–11/08
ページ5に含まれる内容の要旨
ATmega324PA 2. Overview The ATmega324PA is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega324PA achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram PA7..0 PB7..0 VCC Power Supervision RESET PORT A (8) PORT B (8) POR / BOD & RESET Watchdog GND Timer Analog A/D Watchdog
ページ6に含まれる内容の要旨
The ATmega324PA provides the following features: 32K bytes of In-System Programmable Flash with Read-While-Write capabilities, 1K bytes EEPROM, 2K bytes SRAM, 32 general pur- pose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented 2-wire Serial Inter- face, a 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscill
ページ7に含まれる内容の要旨
ATmega324PA 2.2 Pin Descriptions 2.2.1 VCC Digital supply voltage. 2.2.2 GND Ground. 2.2.3 Port A (PA7:PA0) Port A serves as analog inputs to the Analog-to-digital Converter. Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are ac
ページ8に含まれる内容の要旨
2.2.7 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in ”System and Reset Characteristics” on page 329. Shorter pulses are not guaranteed to generate a reset. 2.2.8 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.2.9 XTAL2 Output from the inverting Oscillator amplifier. 2.2.10 AVCC AVCC is the supply voltage pin for
ページ9に含まれる内容の要旨
ATmega324PA 5. Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xFF) Reserved - - - - - - - (0xFE) Reserved - - - - - - - - (0xFD) Reserved - - - - - - - - (0xFC) Reserved - - - - - - - - (0xFB) Reserved - - - - - - - (0xFA) Reserved - - - - - - - - (0xF9) Reserved - - - - - - - (0xF8) Reserved - - - - - - - - (0xF7) Reserved - - - - - - - - (0xF6) Reserved - - - - - - - - (0xF5) Reserved - - - - - - - (0xF4) Reserved - - - - - - - - (0xF3) Reserved - - - - -
ページ10に含まれる内容の要旨
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 190/205 (0xBF) Reserved - - - - - - - - (0xBE) Reserved - - - - - - - - (0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 -236 (0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN -TWIE 233 (0xBB) TWDR 2-wire Serial Interface Data Register 235 (0xBA) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 236 (0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 - TWPS1 TWPS0 235 (0xB8) TWBR 2-wire Serial
ページ11に含まれる内容の要旨
ATmega324PA Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 260 (0x7D) Reserved - - - - - - - - (0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 256 (0x7B) ADCSRB -ACME - - - ADTS2 ADTS1 ADTS0 239 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 258 (0x79) ADCH ADC Data Register High byte 259 (0x78) ADCL ADC Data Register Low byte 259 (0x77) Reserved - - - - - - - - (0x76) Reserved - - - - - - - - (0x7
ページ12に含まれる内容の要旨
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x1C (0x3C) EIFR - - - - - INTF2 INTF1 INTF0 69 0x1B (0x3B) PCIFR - - - - PCIF3 PCIF2 PCIF1 PCIF0 70 0x1A (0x3A) Reserved - - - - - - - - 0x19 (0x39) Reserved - - - - - - - - 0x18 (0x38) Reserved - - - - - - - - 0x17 (0x37) TIFR2 - - - - - OCF2B OCF2A TOV2 160 0x16 (0x36) TIFR1 - -ICF1 - - OCF1B OCF1A TOV1 139 0x15 (0x35) TIFR0 - - - - - OCF0B OCF0A TOV0 110 0x14 (0x34) Reserved - - - - - - - - 0x13 (0x33) Reserved - - - - - - - -
ページ13に含まれる内容の要旨
ATmega324PA 6. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - R
ページ14に含まれる内容の要旨
Mnemonics Operands Description Operation Flags #Clocks BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Log
ページ15に含まれる内容の要旨
ATmega324PA Mnemonics Operands Description Operation Flags #Clocks SPM Store Program Memory (Z) ← R1:R0 None - IN Rd, P In Port Rd ← PNone 1 OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 BREAK Break For On-chip Debug Only None N/A 15 8152AS–AVR
ページ16に含まれる内容の要旨
7. Ordering Information 7.1 ATmega324PA (3) (2) (1) Power Supply Ordering Code Package Operational Range Speed (MHz) ATmega324PA-AU 44A ATmega324PA-PU 40P6 Industrial 20 1.8 - 5.5V ATmega324PA-MU 44M1 o o (-40 C to 85 C) (4) ATmega324PA-MCH 44MC ATmega324PA-CU 49C2 Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction
ページ17に含まれる内容の要旨
ATmega324PA 8. Packaging Information 8.1 44A PIN 1 B PIN 1 IDENTIFIER E1 E e D1 D C 0˚~7˚ A2 A A1 L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 11.75 12.00 12.25 D1 9.90 10.00 10.10 Note 2 E 11.75 12.00 12.25 Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. E1 9.90 10.00 10.10 Note 2 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D
ページ18に含まれる内容の要旨
8.2 40P6 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E COMMON DIMENSIONS (Unit of Measure = mm) 0º ~ 15º REF C MIN MAX SYMBOL NOM NOTE A – – 4.826 eB A1 0.381 – – D 52.070 – 52.578 Note 2 E 15.240 – 15.875 E1 13.462 – 13.970 Note 2 B 0.356 – 0.559 B1 1.041 – 1.651 Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. L 3.048 – 3.556 Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). C 0.203 – 0.381
ページ19に含まれる内容の要旨
ATmega324PA 8.3 44M1 D Marked Pin# 1 ID E SEATING PLANE A1 TOP VIEW A3 A K L Pin #1 Corner SIDE VIEW D2 Pin #1 Option A COMMON DIMENSIONS 1 Triangle 2 (Unit of Measure = mm) 3 SYMBOL MIN NOM MAX NOTE A 0.80 0.90 1.00 E2 Option B A1 – 0.02 0.05 Pin #1 Chamfer A3 0.20 REF (C 0.30) b 0.18 0.23 0.30 D 6.90 7.00 7.10 K D2 5.00 5.20 5.40 Option C Pin #1 Notch b e E 6.90 7.00 7.10 (0.20 R) E2 5.00 5.20 5.40 BOTTOM VIEW e 0.50 BSC L 0.59 0.64 0.69 Note: JEDEC Standard MO-220, Fig. 1 (SAW
ページ20に含まれる内容の要旨
8.4 44MC C Pin 1 ID D SIDE VIEW y A1 E A TOP VIEW eT/2 A19 A24 B20 B16 eR A1 A18 COMMON DIMENSIONS B15 B1 (Unit of Measure = mm) b SYMBOL MIN NOM MAX N O T E 0.40 R0.20 A 0.80 0.90 1.00 D2 A1 0.00 0.02 0.05 b 0.18 0.23 0.30 eT C 0.20 REF B11 B5 D 4.90 5.00 5.10 A6 A13 D2 2.55 2.60 2.65 B10 B6 E 4.90 5.00 5.10 A12 A7 E2 2.55 2.60 2.65 L L L E2 eT – 0.70 – eR – 0.40 – BOTTOM VIEW K 0.45 – – L 0.30 0.35 0.40 1. The terminal #1 ID is
