ページ1に含まれる内容の要旨
TM
AMD Sempron
Processor Model 10
with 256K L2 Cache
Data Sheet
Publication # 31994 Rev. A-1
Issue Date: August 2004
ページ2に含まれる内容の要旨
©2004 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or war- ranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and prod- uct descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
ページ3に含まれる内容の要旨
31994A —1 August 2004 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet Table of Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xi 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 QuantiSpeed™ Architecture Summary. . . . . . . . . . . . . . . . . . . 3 2 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Overview . .
ページ4に含まれる内容の要旨
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31 994A —1 August 2004 7.9 SYSCLK and SYSCLK# DC Characteristics . . . . . . . . . . . . . . 31 7.10 General AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 32 7.11 Open Drain Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.12 Thermal Diode Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35 Thermal Diode Electrical Characteristics. . . . . . . . . . . . . 35 Thermal Pro
ページ5に含まれる内容の要旨
31994A —1 August 2004 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet NMI Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PLL Bypass and Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 SADDIN[1:0]# and SADDOUT[1:0]# Pins . . . . . . . . . . . . . 73 Scan Pin
ページ6に含まれる内容の要旨
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31 994A —1 August 2004 vi Table of Contents
ページ7に含まれる内容の要旨
31994A —1 August 2004 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet List of Figures Figure 1. Typical AMD Sempron™ Processor Model 10 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Symbol Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. AMD Sempron Processor Model 10 Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ページ8に含まれる内容の要旨
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31 994A —1 August 2004 viii List of Figures
ページ9に含まれる内容の要旨
31994A —1 August 2004 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet List of Tables Table 1. Electrical and Thermal Specifications for the AMD Sempron™ Processor Model 10 with 256K L2 Cache . . . . 21 Table 2. 333 FSB SYSCLK and SYSCLK# AC Characteristics. . . . . . . . . 22 Table 3. 333 FSB AMD Athlon™ System Bus AC Characteristics . . . . . . 23 Table 4. 333 FSB AMD Athlon System Bus DC Characteristics . . . . . . . . 24 Table 5. Interface Signal Groupings . . . . . . . . .
ページ10に含まれる内容の要旨
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31 994A —1 August 2004 x List of Tables
ページ11に含まれる内容の要旨
31994A —1 August 2004 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet Revision History Date Rev Description August 2004 A-1 ■ Initial release of the AMD Sempron™ Processor Model 10 Data Sheet Revision History xi
ページ12に含まれる内容の要旨
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31 994A —1 August 2004 xii Revision History
ページ13に含まれる内容の要旨
31994A —1 August 2004 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 1 Overview The AMD Sempron™ processor model 10 with 256K of L2 cache, the new value brand for every-day computing, performs at the top of its class. Using QuantiSpeed™ architecture, this processor is designed to power over 60,000 home and business applications, and it is compatible with various operating ® systems including Linux and all existing Windows operating systems. The AMD Sempron™ processor model
ページ14に含まれる内容の要旨
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31 994A —1 August 2004 The AMD Sempron processor model 10 with 256K of L2 cache is binary-compatible with existing x86 software and backwards compatible with applications optimized for MMX™, SSE, and 3DNow!™ technology. Using a data format and single-instruction multiple-data (SIMD) operation based on the MMX instruction model, the AMD Sempron processor model 10 can produce as many as four, 32-bit, single-precision floating-po
ページ15に含まれる内容の要旨
31994A —1 August 2004 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 1.1 QuantiSpeed™ Architecture Summary The following design features summarize the QuantiSpeed architecture of the AMD Sempron processor model 10 with 256K of L2 cache: ■ A nine-issue, superpipelined, superscalar x86 processor microarchitecture designed for increased instructions per cycle (IPC) and high clock frequencies ■ Pipelined floating-point unit that executes all x87 (floating-point), MMX, SSE and 3D
ページ16に含まれる内容の要旨
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31 994A —1 August 2004 Ther mal Monitor AMD Sempron™ Proces- sor Model 10 AMD Athlon™ System Bus AGP AGP Bus Memory Bus S ystem Controller (Northbridge) SDRAM or DDR PCI Bus Peripheral Bus Con- troller (Southbridge) LAN SCSI Modem / Audio LPC Bus USB Dual EIDE BIOS Figure 1. Typical AMD Sempron™ Processor Model 10 System Block Diagram 4 Overview Chapter 1
ページ17に含まれる内容の要旨
31994A —1 August 2004 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 2 Interface Signals This section describes the interface signals utilized by the AMD Sempron™ processor model 10. 2.1 Overview The AMD Athlon system bus architecture is designed to deliver excellent data movement bandwidth for next-generation x86 platforms as well as the high-performance required by enterprise-class application software. The system bus architecture consists of three high-speed channels (a
ページ18に含まれる内容の要旨
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31 994A —1 August 2004 2.3 Push-Pull (PP) Drivers The AMD Sempron processor model 10 supports push-pull (PP) drivers. The system logic configures the processor with the configuration parameter called SysPushPull (1=PP). The impedance of the PP drivers is set to match the impedance of the motherboard by two external resistors connected to the ZN and ZP pins. See “ZN and ZP Pins” on page 75 for more information. 2.4 AMD Athlon™ S
ページ19に含まれる内容の要旨
{ 31994A —1 August 2004 AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 3 Logic Symbol Diagram Figure 2 is the logic symbol diagram of the processor. This diagram shows the logical grouping of the input and output signals. Clock SYSCLK SYSCLK# VID[4:0] SDATA[63:0]# COREFB SDATAINCLK[3:0]# Voltage COREFB# SDATAOUTCLK[3:0]# Control Data SDATAINVALID# PWROK { SDATAOUTVALID# Frequency FID[3:0] SFILLVALID# Control Front-Side Bus FSB_SENSE[1:0] Autodetect SADDIN
ページ20に含まれる内容の要旨
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet 31 994A —1 August 2004 8 Logic Symbol Diagram Chapter 3
