ページ1に含まれる内容の要旨
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MicroConverter , Multichannel
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12-Bit ADC with Embedded FLASH MCU
ADuC812
FEATURES APPLICATIONS
ANALOG I/O Intelligent Sensors Calibration and Conditioning
8-Channel, High Accuracy 12-Bit ADC Battery Powered Systems (Portable PCs, Instruments,
On-Chip, 100 ppm/C Voltage Reference Monitors)
High-Speed 200 kSPS Transient Capture Systems
DMA Controller for High-Speed ADC-to-RAM Capture DAS and Communications Systems
Two 12-Bit Voltage Output DACs Control Loop Monitors (Optical Networks/Base Sta
ページ2に含まれる内容の要旨
ADuC812 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SERIAL PERIPHERAL INTERFACE . . . . . . . . . . . . . . . . . . . 26 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 MISO (Master In, Slave Out Data I/O Pin), Pin #19 . . . . . . 26 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 MOSI (Master Out, Slave In Pin), Pin #27 . . . . . . . . . . . . . . 26 ABSOLUTE MAXIMUM
ページ3に含まれる内容の要旨
ADuC812 1, 2 (AV = DV = 3.0 V or 5.0 V 10%, REF /REF = 2.5 V Internal Reference, MCLKIN = 11.0592 MHz, SPECIFICATIONS DD DD IN OUT f = 200 kHz, DAC V Load to AGND; R = 2 k, C = 100 pF. All specifications T = T to T , unless otherwise noted.) SAMPLE OUT L L A MIN MAX ADuC812BS Parameter V = 5 V V = 3 V Unit Test Conditions/Comments DD DD ADC CHANNEL SPECIFICATIONS 3, 4 DC ACCURACY Resolution 12 12 Bits Integral Nonlinearity ±1/2 ±1/2 LSB typ f = 100 kHz SAMPLE ±1.5 LSB max f = 100
ページ4に含まれる内容の要旨
1, 2 ADuC812–SPECIFICATIONS (continued) ADuC812BS Parameter V = 5 V V = 3 V Unit Test Conditions/Comments DD DD DAC AC CHARACTERISTICS Voltage Output Settling Time 15 15 µ s typ Full-Scale Settling Time to Within 1/2 LSB of Final Value Digital-to-Analog Glitch Energy 10 10 nV sec typ 1 LSB Change at Major Carry REFERENCE INPUT/OUTPUT 9 REF Input Voltage Range 2.3/V 2.3/V V min/max IN DD DD Input Impedance 150 150 kΩ typ REF Output Voltage 2.5 ±2.5% V min/max Initial Tolerance @ 25°C
ページ5に含まれる内容の要旨
ADuC812 ADuC812BS Parameter V = 5 V V = 3 V Unit Test Conditions/Comments DD DD DIGITAL OUTPUTS Output High Voltage (V ) 2.4 V min V = 4.5 V to 5.5 V OH DD I = 80 µ A SOURCE 4.0 2.6 V typ V = 2.7 V to 3.3 V DD I = 20 µ A SOURCE Output Low Voltage (V ) OL ALE, PSEN, Ports 0 and 2 0.4 V max I = 1.6 mA SINK 0.2 0.2 V typ I = 1.6 mA SINK Port 3 0.4 V max I = 8 mA SINK 0.2 0.2 V typ I = 8 mA SINK Floating State Leakage Current ±10 µ A max ±5 ±5 µ A typ Floating State Output Capacitance 10
ページ6に含まれる内容の要旨
ADuC812 ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION (T = 25°C unless otherwise noted) A AV to DV . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V DD DD AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V DV to DGND, AV to AGND . . . . . . . . . –0.3 V to +7 V DD DD Digital Input Voltage to DGND . . . . . –0.3 V, DV + 0.3 V 52 51 50 49 48 47 46 45 44 43 42 41 40 DD Digital Output Voltage to DGND . . . . –0.3 V, DV + 0.3 V DD 1 39 P1.0/ADC0/T2 P2.7/A15/A23 PIN 1 V to
ページ7に含まれる内容の要旨
ADuC812 PIN FUNCTION DESCRIPTIONS Mnemonic Type Function DV P Digital Positive Supply Voltage, 3 V or 5 V Nominal DD AV P Analog Positive Supply Voltage, 3 V or 5 V Nominal DD C I Decoupling Input for On-Chip Reference. Connect 0.1 µ F between this pin and AGND. REF V I/O Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the REF reference source for the analog-to-digital converter. The nominal internal reference voltage is 2.5 V and this app
ページ8に含まれる内容の要旨
ADuC812 PIN FUNCTION DESCRIPTION (continued) Mnemonic Type Function PSEN O Program Store Enable, Logic Output. This output is a control signal that enables the external program memory to the bus during external fetch operations. It is active every six oscillator periods except during external data memory accesses. This pin remains high during internal program execution. PSEN can also be used to enable serial download mode when pulled low through a resistor on power-up or RESET. ALE O Address Lat
ページ9に含まれる内容の要旨
ADuC812 ARCHITECTURE, MAIN FEATURES 7FH The ADuC812 is a highly integrated true 12-bit data acquisition system. At its core, the ADuC812 incorporates a high- perfor- mance 8-bit (8052-Compatible) MCU with on-chip 2FH reprogrammable nonvolatile Flash program memory control- BANKS BIT-ADDRESSABLE SPACE ling a multichannel (8-input channels), 12-bit ADC. SELECTED (BIT ADDRESSES 0FH–7FH) VIA The chip incorporates all secondary functions to fully support 20H BITS IN PSW 1FH the programmable data acqu
ページ10に含まれる内容の要旨
ADuC812 OVERVIEW OF MCU-RELATED SFRs Power Control SFR Accumulator SFR The Power Control (PCON) register contains bits for power- ACC is the Accumulator register and is used for math opera- saving options and general-purpose status flags as shown in tions including addition, subtraction, integer multiplication and Table II. division, and Boolean bit manipulations. The mnemonics for SFR Address 87H accumulator-specific instructions refer to the Accumulator as A. Power ON Default Value 00H B SFR B
ページ11に含まれる内容の要旨
ADuC812 SPECIAL FUNCTION REGISTERS All registers except the program counter and the four general purpose register banks, reside in the special function register (SFR) area. The SFR registers include control, configuration and data registers that provide an interface between the CPU and other on- chip peripherals. Figure 4 shows a full SFR memory map and SFR contents on Reset. Unoccupied SFR locations are shown dark-shaded in the figure below (NOT USED). Unoccupied locations in the SFR address sp
ページ12に含まれる内容の要旨
ADuC812 ADC CIRCUIT INFORMATION ADC Transfer Function General Overview The analog input range for the ADC is 0 V to V . For this REF The ADC conversion block incorporates a fast, 8-channel, range, the designed code transitions occur midway between 12-bit, single supply A/D converter. This block provides the successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, user with multichannel mux, track/hold, on-chip reference, 5/2 LSBs . . . FS –3/2 LSBs). The output coding is straight calibration feat
ページ13に含まれる内容の要旨
ADuC812 ADCCON1 – (ADC Control SFR #1) The ADCCON1 register controls conversion and acquisition times, hardware conversion modes and power-down modes as detailed below. SFR Address: EFH SFR Power-On Default Value: 20H M0 D1 M1 D C0 K C1 K A0 Q AC Q TC 2 EX Table III. ADCCON1 SFR Bit Designations Bit Name Description ADCCON1.7 MD1 The mode bits (MD1, MD0) select the active operating mode of the ADC ADCCON1.6 MD0 as follows: MD1 MD0 Active Mode 0 0 ADC powered down. 0 1 ADC normal mode 1 0 ADC pow
ページ14に含まれる内容の要旨
ADuC812 ADCCON2 – (ADC Control SFR #2) The ADCCON2 register controls ADC channel selection and conversion modes as detailed below. SFR Address: D8H SFR Power On Default Value: 00H AA DCIDV MCV CON S3 CON C2 S C1 S C0 S CS Table IV. ADCCON2 SFR Bit Designations Location Name Description ADCCON2.7 ADCI The ADC interrupt bit (ADCI) is set by hardware at the end of a single ADC conversion cycle or at the end of a DMA block conversion. ADCI is cleared by hardware when the PC vectors to the ADC Interr
ページ15に含まれる内容の要旨
ADuC812 Driving the A/D Converter ADuC812 The ADC incorporates a successive approximation (SAR) archi- tecture involving a charge-sampled input stage. Figure 7 shows 51 1 AIN0 the equivalent circuit of the analog input section. Each ADC 0.01F conversion is divided into two distinct phases as defined by the position of the switches in Figure 7. During the sampling phase (with SW1 and SW2 in the “track” position) a charge propor- Figure 8. Buffering Analog Inputs tional to the voltage on the ana
ページ16に含まれる内容の要旨
ADuC812 ground, no amplifier can deliver signals all the way to ground when ADuC812 powered by a single supply. Therefore, if a negative supply is V DD available, you might consider using it to power the front-end 2.5V 51 BANDGAP amplifiers. If you do, however, be sure to include the Schottky EXTERNAL REFERENCE VOLTAGE diodes shown in Figure 8 (or at least the lower of the two BUFFER REFERENCE diodes) to protect the analog input from undervoltage conditions. V REF 8 To summarize this section, u
ページ17に含まれる内容の要旨
ADuC812 core. This mode allows the ADuC812 to capture a contiguous 11 11 STOP COMMAND 00000AH sample stream at full ADC update rates (200 kHz). NO CONVERSION RESULT WRITTEN HERE 00 11 A typical DMA Mode configuration example. CONVERSION RESULT To set the ADuC812 into DMA mode a number of steps must FOR ADC CH#3 00 11 be followed. CONVERSION RESULT FOR TEMP SENSOR 10 0 0 1. The ADC must be powered down. This is done by ensuring CONVERSION RESULT MD1 and MD0 are both set to 0 in ADCCON1. 01 0 1 FO
ページ18に含まれる内容の要旨
ADuC812 the gain calibration coefficient is divided into ADCGAINH (6 bits) EPROM EEPROM and ADCGAINL (8 bits).The offset calibration coefficient compen- TECHNOLOGY TECHNOLOGY sates for dc offset errors in both the ADC and the input signal. SPACE EFFICIENT/ IN-CIRCUIT Increasing the offset coefficient compensates for positive offset, DENSITY REPROGRAMMABLE and effectively pushes the ADC Transfer Function DOWN. FLASH/EE MEMORY Decreasing the offset coefficient compensates for negative offset, TECH
ページ19に含まれる内容の要旨
ADuC812 Using the Flash/EE Program Memory Using the Flash/EE Data Memory This 8K Byte Flash/EE Program Memory array is mapped The user Flash/EE data memory array consists of 640 bytes that into the lower 8K bytes of the 64K bytes program space addres- are configured into 160 (Page 00H to Page 9FH), 4-byte pages sable by the ADuC812 and will be used to hold user code in as shown in Figure 16. typical applications. 9FH BYTE 1 BYTE 2 BYTE 3 BYTE 4 The program memory array can be programmed in one o
ページ20に含まれる内容の要旨
ADuC812 ECON—Flash/EE Memory Control SFR Using the Flash/EE Memory Interface This SFR acts as a command interpreter and may be written As with all Flash/EE memory architectures, the array can be pro- with one of five command modes to enable various read, pro- grammed in system at a byte level, although it must be erased gram and erase cycles as detailed in Table VII: first, the erasure being performed in page blocks (4-byte pages in this case). Table VII. ECON–Flash/EE Memory Control Register A
