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TMS320DM647/DM648
Video Port/VCXO Interpolated Control (VIC)
Port
User's Guide
Literature Number: SPRUEM1
May 2007
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2 SPRUEM1–May 2007 Submit Documentation Feedback
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Contents Preface.............................................................................................................................. 13 1 Overview ................................................................................................................. 16 1.1 Video Port ................................................................................................................ 17 1.2 Video Port FIFO............................................................................
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3.3.3 Y/C Image Window and Capture ............................................................................. 50 3.3.4 Y/C FIFO Packing .............................................................................................. 51 3.4 BT.656 and Y/C Mode Field and Frame Operation.......................................................... 51 3.4.1 Capture Determination and Notification ..................................................................... 52 3.4.2 Vertical Synchronization ...
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3.13.14 TCI System Time Clock LSB Register (TCISTCLKL) ................................................... 86 3.13.15 TCI System Time Clock MSB Register (TCISTCLKM).................................................. 87 3.13.16 TCI System Time Clock Compare LSB Register (TCISTCMPL) ...................................... 88 3.13.17 TCI System Time Clock Compare MSB Register (TCISTCMPM)..................................... 88 3.13.18 TCI System Time Clock Compare Mask LSB Register (TCISTMSKL) ......
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4.12 Video Display Registers ........................................................................................... 122 4.12.1 Video Display Status Register (VDSTAT) ................................................................ 122 4.12.2 Video Display Control Register (VDCTL) ................................................................. 123 4.12.3 Video Display Frame Size Register (VDFRMSZ)........................................................ 127 4.12.4 Video Display Horizontal B
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6.3 Operational Details .................................................................................................. 169 6.4 Enabling VIC Port .................................................................................................... 170 6.5 VIC Port Registers ................................................................................................... 170 6.5.1 VIC Control Register (VICCTL).............................................................................. 171 6
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List of Figures 1-1 Video Port Block Diagram................................................................................................. 18 1-2 BT.656 Video Capture FIFO Configuration ............................................................................. 20 1-3 8-Bit Raw Video Capture and TCI Video Capture FIFO Configuration.............................................. 21 1-4 Y/C Video Capture FIFO Configuration .......................................................................
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3-39 TCI System Time Clock Compare Mask MSB Register (TCISTMSKM) ............................................ 90 3-40 TCI System Time Clock Ticks Interrupt Register (TCITICKS)........................................................ 90 4-1 NTSC Compatible Interlaced Display.................................................................................... 93 4-2 SMPTE 296M Compatible Progressive Scan Display................................................................. 94 4-3 Interlaced Blank
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4-52 Video Display Event Register (VDDISPEVT) ......................................................................... 142 4-53 Video Display Clipping Register (VDCLIP)............................................................................ 143 4-54 Video Display Default Display Value Register (VDDEFVAL) ....................................................... 144 4-55 Video Display Default Display Value Register (VDDEFVAL) - Raw Data Mode ................................. 144 4-56 Video Dis
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List of Tables 1-1 Video Capture Signal Mapping........................................................................................... 26 1-2 Video Display Signal Mapping............................................................................................ 26 1-3 VDIN Data Bus Usage for Capture Modes ............................................................................. 27 1-4 VDOUT Data Bus Usage for Display Modes ................................................................
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4-5 Video Display Control Registers ....................................................................................... 122 4-6 Video Display Status Register (VDSTAT) Field Descriptions....................................................... 123 4-7 Video Display Control Register (VDCTL) Field Descriptions........................................................ 124 4-8 Video Display Frame Size Register (VDFRMSZ) Field Descriptions .............................................. 127 4-9 Video D
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Preface SPRUEM1–May 2007 Read This First About This Manual This document describes the video port and VCXO interpolated control (VIC) port in the digital signal processors (DSPs). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. • Registers in this document are shown in figures and described in tables. – Each register figure shows a rectangle divided into
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www.ti.com Related Documentation From Texas Instruments SPRUEK8 —TMS320DM647/DM648 DSP Inter-Integrated Circuit (I2C) Module User's Guide describes the inter-integrated circuit (I2C) peripheral in the TMS320DM647/DM648 Digital Signal Processor (DSP). The I2C peripheral provides an interface between the DSP and other devices compliant with the I2C-bus specification and connected by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit and receive up to 8-bit wide
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www.ti.com Related Documentation From Texas Instruments SPRUEM2 —TMS320DM647/DM648 DSP Serial Port Interface (SPI) User's Guide discusses the Serial Port Interface (SPI) in the TMS320DM647/DM648 Digital Signal Processor (DSP). This reference guide provides the specifications for a 16-bit configurable, synchronous serial peripheral interface. The SPI is a programmable-length shift register, used for high speed communication between external peripherals or other DSPs. Trademarks SPRUEM1–May 2007 R
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SPRUEM1–May 2007 Overview This chapter provides an overview of the video port peripheral in the digital signal processors (DSPs). An overview of the video port functions, FIFO configurations, and signal mapping are included. Topic .................................................................................................. Page 1.1 Video Port................................................................................ 17 1.2 Video Port FIFO ...............................................
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www.ti.com Video Port 1.1 Video Port The video port peripheral can operate as a video capture port, video display port, or transport channel interface (TCI) capture port. It provides the following functions: • Video capture mode: – Capture rate of up to 80 MHZ. – Two channels of 8-bit digital video input from a digital camera or an analog camera (using a video decoder). Digital video input is in YCbCr 4:2:2 format with 8-bit resolution multiplexed in ITU-R BT.656 format. – One channel of Y/C 16-
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www.ti.com Video Port This document describes the full feature set offered by the video port. See the device-specific datasheet for details about I/O timing information. Figure 1-1. Video Port Block Diagram Internal peripheral bus 32 Memory VCLK1 VCLK2 mapped Timing and VCTL1 DMA interface registers control logic VCTL2 VCTL3 64 BT.656 capture BT.656 display 8 8 pipeline pipeline Y/C video Y/C video VDIN[19−2] VDOUT[19−2] 16 capture pipeline Capture/display 16 display pipeline buffer 16 16 Raw v
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www.ti.com Video Port FIFO 1.2 Video Port FIFO The video port includes a FIFO to store data coming into or out from the video port. The video port operates in conjunction with EDMA transfers to move data between the video port FIFO and external or on-chip memory. You can program threshold settings so that EDMA events generate when the video port FIFO reaches a certain fullness (for capture) or goes below a certain fullness (for display). You set up EDMA Channels that are required to service the
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www.ti.com Video Port FIFO 1.2.2 Video Capture FIFO Configurations During video capture operation, the video port FIFO has one of four configurations depending on the capture mode. For BT.656 operation, the FIFO is split into channel A and B, as shown in Figure 1-2. Each FIFO is clocked independently with the channel A FIFO receiving data from the VDIN[9-2] half of the bus and the channel B FIFO receiving data from the VDIN[19-12] half of the bus. Each channel's FIFO is further split into Y, Cb,
