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®
Intel 31244 PCI-X to Serial ATA
Controller
Design Guide
April 2004
Order Number: 273651-003
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® Intel 31244 PCI-X to Serial ATA Controller INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTELR PRODUCTS. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTU
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® Intel 31244 PCI-X to Serial ATA Controller Contents Contents 1 About This Document ......................................................................................................................9 1.1 Reference Documentation ....................................................................................................9 1.2 Terminology and Definitions .................................................................................................9 2 Overview........................
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® Intel 31244 PCI-X to Serial ATA Controller Contents 7.3 PCI General Layout Guidelines .......................................................................................... 49 7.4 PCI-X Layout Guidelines For Slot Configurations...............................................................50 7.4.1 Protection Circuitry for Add-in Cards .....................................................................50 7.4.2 PCI Clock Layout Guidelines....................................................
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® Intel 31244 PCI-X to Serial ATA Controller Contents Figures ® 1Intel 31244 PCI-X to Serial ATA Controller Block Diagram......................................................14 2 Quad Serial ATA Host Bus Adapter............................................................................................15 3 Packaging Considerations..........................................................................................................17 4 Package Information: 256-pin PBGA.......................
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® Intel 31244 PCI-X to Serial ATA Controller Contents Tables 1 Reference Documents.................................................................................................................. 9 2 Terminology and Definition........................................................................................................... 9 3 Serial ATA Signals Pin Descriptions...........................................................................................18 4 PCI-X Bus Pin Descriptions....
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® Intel 31244 PCI-X to Serial ATA Controller Contents Revision History Date Revision # Description April 2004 003 Removed Section 5.4.5, “Spread Spectrum Clocking” on page 35. Removed SSC pin in Table 2, “Terminology and Definition” on page 9. Updated SSCEN pin in Table 5, “Configuration Pin Descriptions” on page 20 and Table 30, “Terminations: Pull-up/Pull-down” on page 65. Removed Section 9.1, “Power Delivery for the Intel® 31244 PCI-X to Serial ATA Controller (TBD)” on page 59. ® In Appendi
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® Intel 31244 PCI-X to Serial ATA Controller Contents This page intentionally left blank. 8 Design Guide
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About This Document 1 1.1 Reference Documentation For the latest revision and documentation number, contact your Intel representative. Table 1. Reference Documents Document Intel Document Number or Source ® Intel Artisea PCI-X to Serial ATA Controller Developer’s Manual 273603 ® Intel Artisea PCI-X to Serial ATA Controller Datasheet 273595 ® Intel Packaging Databook 240800 298179 Printed Circuit Board (PCB)Test Methodology User’s Guide, http://developer.intel.com/design/chipsets/ Revision 1.6 a
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® Intel 31244 PCI-X to Serial ATA Controller About This Document Table 2. Terminology and Definition (Sheet 2 of 3) Term Definition Printed circuit board. Layer 1: copper Example manufacturing process consists of Prepreg the following steps: Layer 2: GND Consists of alternating layers of core and prepreg stacked Core The finished PCB is heated and cured. PCB Layer 3: VCC The via holes are drilled Prepreg Layer 4: copper Plating covers holes and outer surfaces Etching removes unwant
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® Intel 31244 PCI-X to Serial ATA Controller About This Document Table 2. Terminology and Definition (Sheet 3 of 3) Term Definition RxData Serially encoded 10b data attached to the high-speed serial differential line receiver. The 8B/10B encoding scheme transmits eight bits as a 10-bit code group. This encoding is 10b encoding used with Gigabit Ethernet, Fibre Channel and InfiniBand*. Jitter Jitter is a high-frequency, semi-random displacement of a signal from its ideal location. Inter-symbol
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® Intel 31244 PCI-X to Serial ATA Controller About This Document This page left intentionally blank. 12 Design Guide
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® Intel 31244 PCI-X to Serial ATA Controller Overview Overview 2 This document provides layout information and guidelines for designing platform or add-in board ® applications with the Intel 31244 PCI-X to serial ATA controller (GD31244). It is recommended that this document be used as a guideline. Intel recommends employing best-known design practices with board-level simulation, signal integrity testing and validation for a robust design. Designers should note that this guide focuses upon s
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® Intel 31244 PCI-X to Serial ATA Controller Overview Feature Highlights: Four SATA Channels at 1.5 Gbits/s Serial ATA: High speed Serialized AT Attachment Specification, Revision 1.0e Compliant 64-bit/133 MHz PCI-X Bus. Backwards compatible to 32-bit/33 MHz and 64-bit/66 MHz Compatible with existing Operating Systems Supports native PCI IDE Hot-Plug Drives Supports Master/Slave Mode for Compatibility with existing Operating Systems Supports SATA Direct Port Access (Master/Master
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2.2 Applications The GD31244 may be used to build a Serial ATA Host Bus Adapter which connects to the PCI-X bus. Control for external activity LEDs, a 37.5 MHz Crystal, a voltage regulator and some external resistors and capacitors are needed. Figure 2. Quad Serial ATA Host Bus Adapter 3.3V 2.5V Regulator VIO VCC P_AD[63:0] + LED0 P_CBE[7:0] 22µF, LED1 TANT, P_PAR EIA-A, LED2 P_PAR64 6.3V LED3 P_FRAME# .1µF, P_TRDY# 0603, CAP0 P_IRDY# x7R 0.1 µF P_STOP# CAP1 10 µH 20Ω P_DEVSEL# 0603, 1% P_REQ
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® Intel 31244 PCI-X to Serial ATA Controller Overview This page left intentionally blank. 16 Design Guide
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® Intel 31244 PCI-X to Serial ATA Controller ® Intel 31244 PCI-X to Serial ATA Controller Package ® Intel 31244 PCI-X to Serial ATA Controller Package 3 The GD31244 signals, are located on a 256-pin Plastic Ball Grid Array (PBGA) package to simplify ® signal routing and system implementation. For detailed signal descriptions refer to the Intel 31244 PCI-X to Serial ATA Controller Datasheet. Contact your Intel sales representative to obtain a copy of this document. The construction of the pac
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® Intel 31244 PCI-X to Serial ATA Controller ® Intel 31244 PCI-X to Serial ATA Controller Package 3.1 Signal Pin Descriptions The signal pin descriptions for the GD31244 are provided as a reference. A complete list is also ® available in the Intel 31244 PCI-X to Serial ATA Controller Datasheet. Table 3. Serial ATA Signals Pin Descriptions Name Description TX0P, TX0N, TX1P, TX1N, OUTPUT - Differential High-Speed Outputs: These are the differential serial outputs for TX2P, TX2N, each channel. W
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® Intel 31244 PCI-X to Serial ATA Controller ® Intel 31244 PCI-X to Serial ATA Controller Package Table 4. PCI-X Bus Pin Descriptions (Sheet 1 of 2) Name Description Analog: An external 0.015 µF (+/- 10%) capacitor is connected between these pins to set CAP2, CAP3 the PCI PLL loop filter response. BIDIRECTIONAL - LVTTL: Indicates that the device has positively decoded its address as P_ACK64# the target of the current access and the target is willing to transfer data using the full 64-bit data
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® Intel 31244 PCI-X to Serial ATA Controller ® Intel 31244 PCI-X to Serial ATA Controller Package Table 4. PCI-X Bus Pin Descriptions (Sheet 2 of 2) Name Description BIDIRECTIONAL - LVTTL: Indicates the attempt of a 64-bit transaction on the PCI bus. P_REQ64# When the target is 64-bit capable, the target acknowledges the attempt with the assertion of P_ACK64#. INPUT - LVTTL Reset: This signal is used to place PCI-X registers, sequencers, and P_RST# signals into a consistent state. When P_RST#
