ページ1に含まれる内容の要旨
FUJITSU MICROELECTRONICS
DS04–21348–3Ea
DATA SHEET
ASSP
Single Serial Input
PLL Frequency Synthesizer
On-Chip prescaler
MB15C02
■ DESCRIPTION
The Fujitsu Microelectronics MB15C02 is a serial input Phase Locked Loop (PLL) frequency synthesizer with a
prescaler. A 64/65 division is available for the prescaler that enables pulse swallow operation.
This operates with a supply voltage of 1.0 V (min.).
MB15C02 is suitable for mobile communications, such as paging systems.
■ FEATURES
• High frequenc
ページ2に含まれる内容の要旨
MB15C02 ■ PIN ASSIGNMENTS SSOP-20 pin VDD VSS 1 20 Clock OSCIN 2 19 NC NC 18 3 Data OSCOUT 4 17 Top LE TEST 16 5 View fin 6 FC 15 PS 7 φP 14 NC NC 8 13 φR LD 9 12 Do Vp 11 10 (FPT-20P-M03) SSOP-16 pin VSS VDD 1 16 Clock OSCIN 2 15 OSCOUT Data 3 14 LE TEST 4 13 Top fin FC 5 12 View φP PS 6 11 LD φR 7 10 Do Vp 8 9 (FPT-16P-M05) 2
ページ3に含まれる内容の要旨
MB15C02 ■ PIN DESCRIPTIONS Pin no. Pin I/O Descriptions SSOP SSOP name 16 20 1 1 VDD – Power supply voltage Clock input for the shift register.(Schmitt trigger input) 2 2 Clock I Data is shifted into the shift register on the rising edge of the clock. – 3 NC – No connection 3 4 Data I Serial data input using binary code.(Schmitt trigger input) Load enable signal input (Schmitt trigger input) 4 5 LE I When LE is high, the data in the shift register is transferred to a latch, according to the c
ページ4に含まれる内容の要旨
MB15C02 (Continued) Pin no. Pin I/O Descriptions SSOP SSOP name 16 20 Oscillator output. 14 17 OSCOUT O Connection for an external crystal. – 18 NC – No connection Programmable reference divider input. Oscillator input. 15 19 OSCIN I Clock can be input to OSCIN from outside. In the case, please leave OSCOUT pin open and make connection with OSCIN as AC coupling. 16 20 VSS – Ground pin. 4
ページ5に含まれる内容の要旨
MB15C02 ■ BLOCK DIAGRAM Crystal oscillator VDD VSS circuit Programmable reference divider OSCIN Binary 14-bit reference counter Intermittent mode control 14 circuit OSCOUT 14-bit latch fr Clock Phase TEST comparator fp 14 FC Output 18-bit shift register φP control Data Control circuit register 18 LE Output control 18-bit latch φR circuit 6 12 fin Binary 6-bit Binary 12-bit PS Charge Prescaler swallow programma- VP pump counter ble counter LD Control circuit Lock detector Do 5
ページ6に含まれる内容の要旨
MB15C02 ■ ABSOLUTE MAXIMUM RATINGS Rating Parameter Symbol Unit Remark Min. Max. Power supply voltage VDD, VP GND–0.5 +2.0 V Input voltage VIN GND–0.5 VDD +0.5 V Output voltage VOUT GND–0.5 VDD +0.5 V Output current IOUT –10 +10 mA Storage temperature Tstg –40 +125 °C WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Val
ページ7に含まれる内容の要旨
MB15C02 ■ ELECTRICAL CHARACTERISTICS (For 220 MHz :VDD = Vp = 1.0 to 1.5 V, Ta = –20 to +60°C) (For 330 MHz :VDD = Vp = 1.2 to 1.5 V, Ta = –20 to +60°C) (For 450 MHz :VDD = Vp = 1.3 to 1.5 V, Ta = –20 to +60°C) Value Parameter Symbol Condition Unit *3 *4 Min. Typ. Max. – 0.6 1.2 (VDD=1.0V/220MHz) *1 Power supply current Active Mode (VDD=1.2V/330MHz) – 1.0 1.8 mA IDD (VDD=1.3V/450MHz) – 1.3 2.2 – 50 250 (VDD=1.0V) Power sav- *2 Power saving current (VDD=1.2V) – 70 300 µA IDDS ing mode (VDD=1.3V
ページ8に含まれる内容の要旨
MB15C02 ■ FUNCTION DESCRIPTIONS 1. Pulse Swallow Function The divide ratio can be calculated using the following equation: fVCO = [(M × N) + A] × fOSC ÷ R (A < N) fVCO : Output frequency of external voltage controlled oscillator (VCO) N : Preset divide ratio of binary 12-bit programmable counter (5 to 4,095) A : Preset divide ratio of binary 6-bit swallow counter (0 to 63) fOSC : Output frequency of the reference frequency oscillator R : Preset divide ratio of binary 14-bit programmable refere
ページ9に含まれる内容の要旨
MB15C02 Divide ratio range: Prescaler : M = 64, M+1=65 Swallow counter : A = 0 to 63 Programmable counter : N = 5 to 4095 The MB15C02 uses the pulse swallow method; consequently, the divide rations of the swallow and programmable counters must satisfy the relationship N>A. The total divide ratio of the programmable divider is calculated as follows: Total divide ratio = (M + 1) × A + M × (N – A) = M × N + A = 64 × N + A When N is set within 5
ページ10に含まれる内容の要旨
MB15C02 (b) Charge pump The charge pump is available in two forms: internal external. Internal charge pump output (Do) External charge pump outputs (φR, φP) (c) Phase comparator input/output waveforms The phase comparator outputs logic levels summarized in Table 1, according to the phase error between fr and fp. Note that φP is an Nch open drain output. The pulse width of the phase comparator outputs are identical and equal to the phase error between fr and fp as shown in Figure 1. fr fp When FC
ページ11に含まれる内容の要旨
MB15C02 (d) Lock detector The lock detector detects the lock and unlock states of the PLL. The lock detector outputs “H” when the PLL enters the lock state and outputs “L” when the PLL enters the unlock state as shown in Figure 2. When PS = “L”, the lock detector outputs “H” compulsorily. fr fp LD Figure 2. Phase comparator input/output waveforms (Lock detector) 11
ページ12に含まれる内容の要旨
MB15C02 4. Setting the Divide Ratio (1) Serial data format The format of the serial data is shown is Figure 3. The serial data is composed of a control bit and divide ratio setting data. The control bit selects the programmable divider or programmable reference divider. In case of the programmable divider, serial data consists of 18 bits(6 bits for the swallow counter and 12 bits for the programmable counter) and 1 control bit as shown in Figure 3.1. In case of the programmable reference divide
ページ13に含まれる内容の要旨
MB15C02 (2) The flow of serial data Serial data is received via data pin in synchronization with the clock input and loaded into shift register which contains the divide ratio setting data and into the control register which contains the control bit. The logical product (through the AND gate in Figure 4) of LE and the control register output (i.e., control bit) is fed to the enable input of the latches. Accordingly, when LE is set high, the latch for the divider identified by the control bit is
ページ14に含まれる内容の要旨
MB15C02 (4) Setting the divide ratio for the programmable reference divider Columns R0-R13 of Table 3 represent the divide ratio of the programmable reference counter. The control bit is set to 1. Table.3 Divide ratio for the programmable reference divider Divide R R R R R R R R R R R R R R ratio 0 1 2 3 4 5 6 7 8 9 10 11 12 13 (R) 5 1 0100 00000 0000 6 0 1100 00000 0000 ⋅ ⋅⋅⋅ ⋅⋅⋅⋅⋅ ⋅⋅⋅⋅ ⋅⋅ 16383 1 1111 11111 1111 (5) Setting data input timing The MB15C02 uses 19 bits of serial data for the prog
ページ15に含まれる内容の要旨
MB15C02 Since the divide rations are unpredictable when the MB15C02 is turned on, it is necessary to initialize the divide ratio for both dividers at power-on time. As shown in Figure 6, after setting the divide ratio for one of the dividers (e.g., programmable reference divider), set LE to “H” level before setting the divide ratio for the other dividers (e.g., programmable divider). To change the divide ratio of one of the divider after initialization, input the serial data only for that divide
ページ16に含まれる内容の要旨
MB15C02 ■ TYPICAL CHARACTERISTICS 1. fin Input Sensitivity fin input frequency vs. Input sensitivity 20.0 Ta = +25°C 10.0 0.0 −10.0 −20.0 −30.0 −40.0 V DD = 1.0 V V DD = 1.2 V −50.0 V DD = 1.3 V V DD = 1.5 V −60.0 0 100 200 300 400 500 600 700 800 900 1000 fin input frequency (MHz) 2. OSCIN Input Sensitivity OSC IN input frequency vs. Input sensitivity 20.0 Ta = +25°C 10.0 0.0 −10.0 −20.0 −30.0 −40.0 V DD = 1.0 V V DD = 1.2 V −50.0 V DD = 1.3 V V DD = 1.5 V −60.0 0 50 100 150 200 250 300 350 400
ページ17に含まれる内容の要旨
MB15C02 3. fin Power Supply Voltage Power supply voltage vs. fin input frequency (MHz) 1000 Ta = +25°C Vfin = −2.0 (dBm) 900 800 700 600 500 400 300 200 100 0 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Power supply voltage (V) 4. OSCIN Power Supply Voltage Power supply voltage vs. OSC IN input frequency 500 Ta = +25°C Vfin = −2.0 (dBm) 450 400 350 300 250 200 150 100 50 0 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Power supply voltage (V) 17 Input frequency (MHz) Input frequency (MHz)
ページ18に含まれる内容の要旨
MB15C02 5. IDD Power Supply Current Input frequency vs. power supply current 5.0 Ta = +25°C 4.5 4.0 3.5 3.0 2.5 2.0 1.5 V DD = 1.0 V 1.0 V DD = 1.2 V V DD = 1.3 V 0.5 V DD = 1.5 V 0.0 0 100 200 300 400 500 600 700 800 900 1000 Input frequency (MHz) 18 I DD (mA)
ページ19に含まれる内容の要旨
MB15C02 6. Do (Charge Pump) Power Supply Voltage V DD (V p) vs. I OL (at V OL = 0.2 V) 5.0 Ta = +25°C 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 V DD (V) V DD (V p) vs. I OH (at V OH = V DD – 0.2 V) –5.0 Ta = +25°C –4.5 –4.0 –3.5 –3.0 –2.5 –2.0 –1.5 –1.0 –0.5 0.0 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 V DD (V) 19 I OH (mA) I OL (mA)
ページ20に含まれる内容の要旨
MB15C02 7. Spectrum Wave Form ATTEN 10 dB UAUG 16 ∆ MKR −85.50 dB RL 0 dBm 10dB/ 25.0 kHz • LOCK Frequency : 286.0 MHz (fr = 25 kHz) • V DD = 1.2 V, V p = 1.2 V ∆ MKR Ta = +25°C 25.0 kHz D −85.50 dB S CENTER 286.0000 MHz SPAN 200.0 kHz *RBW 1.0 kHz VBW 1.0 kHz *SWP 1.00 s ATTEN 10 dB UAUG 50 ∆ MKR −53.84 dB RL 0 dBm 10dB/ 800 Hz • LOCK Frequency : 286.0 MHz ( fr = 25 kHz) • VDD = 1.2 V, V p = 1.2 V ∆ MKR Ta = +25°
