ページ1に含まれる内容の要旨
INTEGRATED CIRCUITS
DATA SHEET
UDA1325
Universal Serial Bus (USB) CODEC
1999 May 10
Preliminary specification
File under Integrated Circuits, IC01
ページ2に含まれる内容の要旨
Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 FEATURES Audio recording channel • One isochronous input endpoint General • Supports multiple audio data formats (8, 16 and 24 bits) • High Quality USB-compliant Audio/HID device • Twelve selectable sample rates (4, 8, 16 or 32 kHz; • Supports 12 Mbits/s serial data transmission 5.5125, 11.025, 22.05 or 44.1 kHz; 6, 12, 24 or 48 kHz) • Fully USB Plug and Play operation via analog PLL (APLL). • Supports ‘Bus-
ページ3に含まれる内容の要旨
Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 2 2 2 APPLICATIONS All I S inputs and I S outputs support standard I S-bus format and the LSB justified serial data format with word • USB monitors lengths of 16, 18 and 20 bits. • USB speakers 2 Via the digital I/O module with its I S input and output, an • USB microphones external DSP can be used for adding extra sound • USB headsets processing features for the audio playback channel. • USB telephone/answe
ページ4に含まれる内容の要旨
Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies V supply voltage periphery 4.75 5.0 5.25 V DDE V supply voltage core 3.0 3.3 3.6 V DDI I total supply current - 60 tbf mA DD(tot) I total supply current in power-saving note 1 - 360 -μA DD(tot)(ps) mode Dynamic performance DAC (THD + N)/S total harmonic distortion plus f = 44.1 kHz; R =5kΩ s L noise-to-signal ratio f = 1 kHz (0 dB)
ページ5に含まれる内容の要旨
Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 BLOCK DIAGRAM handbook, full pagewidth CLK D+ D- P0.7 to P0.0 P2.0 to P2.7 27 8 (9) 6 (8) 7, 5, 3, 64, 14, 16, 18, 20, V (10) 9 DDI 62, 60, 58, 56 22, 23, 29, 30 V (11) 10 SSI V 24 (19) SSX V (12) 11 SSE XTAL1b 25 (20) ANALOG FRONT-END V OSC (13) 12 DDE XTAL2b 26 (21) TIMING 48 MHz V (23) 32 DDO V 28 (22) DDX V (24) 33 SSO V 52 (39) DDA3 V (29) 38 DDA1 XTAL2a 53 (40) V (30) 39 SSA1 OSC ANALOG USB-PROCESSOR X
ページ6に含まれる内容の要旨
Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 PINNING PIN PIN SYMBOL I/O DESCRIPTION QFP64 SDIP42 GP3/WSO 1 5 I/O general purpose pin 3 or word select output GP4/BCKO 2 6 I/O general purpose pin 4 or bit clock output P0.5 3 - I/O Port 0.5 of the microcontroller SHTCB 4 7 I shift clock of the test control block (active HIGH) P0.6 5 - I/O Port 0.6 of the microcontroller D- 6 8 I/O negative data line of the differential data bus, conforms to the USB standa
ページ7に含まれる内容の要旨
Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 PIN PIN SYMBOL I/O DESCRIPTION QFP64 SDIP42 V 38 29 - analog supply voltage 1 DDA1 V 39 30 - analog ground 1 SSA1 V 40 31 O reference voltage output DAC ref(DA) V 41 32 O reference voltage output ADC ref(AD) V 42 33 - analog supply voltage 2 DDA2 VINL 43 34 I input signal left channel PGA V 44 35 - analog ground 2 SSA2 n.c. 45 -- not connected n.c. 46 -- not connected VINR 47 36 I input signal right channel
ページ8に含まれる内容の要旨
Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 handbook, full pagewidth GP3/WSO 1 51 VRP GP4/BCKO 2 50 ALE P0.5 3 49 VRN SHTCB 4 48 EA P0.6 5 47 VINR D- 6 46 n.c. P0.7 7 45 n.c. D+ 8 44 V SSA2 V 9 43 VINL DDI V 10 UDA1325H 42 V SSI DDA2 V 11 41 V SSE ref(AD) V 12 40 V DDE ref(DA) GP1/DI 13 39 V SSA1 P2.0 14 38 V DDA1 GP5/WSI 15 37 VOUTR P2.1 16 36 RTCB GP0/BCKI 17 35 TC P2.2 18 34 VOUTL SCL 19 33 V SSO MGL349 Fig.2 Pin configuration (QFP64 package). 199
ページ9に含まれる内容の要旨
Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 FUNCTIONAL DESCRIPTION The Universal Serial Bus (USB) Data and power is transferred via the USB over a 4-wire cable. The signalling occurs over two wires and point-to-point segments. The signals on each segment are differentially driven into a cable of 90 Ω intrinsic impedance. The differential receiver features input sensitivity of at least 200 mV and sufficient common mode rejection. handbook, halfpage 1 4
ページ10に含まれる内容の要旨
Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 Memory Management Unit (MMU) and integrated RAM The Analog-to-Digital Interface (ADIF) The MMU and integrated RAM handle the temporary data The ADIF is used for sampling an analog input signal from storage of all USB packets that are received or sent over a microphone or line input and sending the audio samples the bus. to the USB interface. The ADIF consists of a stereo Programmable Gain Amplifier (PGA), a
ページ11に含まれる内容の要旨
Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 The clock source of the analog-to-digital interface The clock source of the ADIF is the analog PLL or the ADC oscillator. The preferred clock source can be selected. The ADC clock used for the ADC and decimation filters is obtained by dividing the clock signal coming from the analog PLL or from the ADC oscillator by a factor Q. Using the analog PLL the user can select 3 basic APLL clock frequencies (see Tabl
ページ12に含まれる内容の要旨
Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 The Asynchronous Digital-to-Analog Converter Table 4 Frequency domains for audio processing by the (ADAC) DSP The ADAC receives audio data from the USB processor or DOMAIN SAMPLE FREQUENCY (kHz) from the digital I/O-bus. The ADAC is able to reconstruct 1 5 to 12 the sample clock from the rate at which the audio samples 212to25 arrive and handles the audio sound processing. After the 325to40 processing, the a
ページ13に含まれる内容の要旨
Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 USB ENDPOINT DESCRIPTION The UDA1325 has following six endpoints: • USB control endpoint 0 • USB control endpoint 1 • USB status interrupt endpoint 1 • USB status interrupt endpoint 2 • Isochronous data sink endpoint • Isochronous data source endpoint. Table 5 Endpoint description ENDPOINT ENDPOINT MAX. PACKET ENDPOINT TYPE DIRECTION NUMBER INDEX SIZE (BYTES) 0 0 control (default) out 8 1in8 1 2 control out
ページ14に含まれる内容の要旨
Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 Table 6 Selection of data transfer type BIT1 BIT0 DATA TRANSFER TYPE 0 0 audio feature registers (volume left, volume right, bass and treble) 0 1 not used 1 0 control registers 1 1 not used Data bits 7 to 2 represent a 6-bit device address, with bit 7 being the MSB and bit 2 the LSB. The address of the ADAC is 000101 (bits 7 to 2). In the event that the ADAC receives a different address, it will deselect its
ページ15に含まれる内容の要旨
Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 Table 7 ADAC audio feature registers BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 REGISTER 0 0 VR5 VR4 VR3 VR2 VR1 VR0 volume right 0 1 VL5 VL4 VL3 VL2 VL1 VL0 volume left 1 0 X BB4 BB3 BB2 BB1 BB0 bass 1 1 X TR4 TR3 TR2 TR1 TR0 treble The sequence for controlling the ADAC audio feature registers via the L3-bus is given in the figure below. DATA_TRANSFER_TYPE DEVICE ADDRESS = $5 dbook, full pagewidth (L3_MODE = L
ページ16に含まれる内容の要旨
Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 Table 8 ADAC general control registers REGISTER BIT DESCRIPTION VALUE COMMENT Control register 0 0 reset ADAC 0 = not reset 1 = reset 1 soft mute control 0 = not muted 1 = mutes 2 synchronous/asynchronous 0 = asynchronous select 0 1 = synchronous 3 channel manipulation 0 = L -> L, R -> R 1=L->R, R->L 4 de-emphasis 0 = de-emphasis off 1 = de-emphasis on 6 and 5 audio mode 00 = flat mode 01 = min. mode 10 = min
ページ17に含まれる内容の要旨
Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 Volume control The volume of the UDA1325 can be controlled from 0 dB down to - 60 dB (in steps of 1 dB). Below - 60 dB the audio signal is muted (-∞ dB). The setting of 0 dB is always referenced to the maximum available volume setting. Independant volume control of the left and right channel is possible (balance control). Table 9 Volume settings right playback channel VR5 VR4 VR3 VR2 VR1 VR0 VOLUME (dB) 0000
ページ18に含まれる内容の要旨
Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 Treble control For the playback channel, treble can be regulated in three audio modes: minimum, flat and maximum mode. In flat mode the audio is not influenced. In minimum and maximum mode, the treble range is from 0 to 6 dB in steps of 2 dB. The programmable treble filter is implemented digitally and has a fixed corner frequency of 3000 Hz for the minimum mode and 1500 Hz for the maximum mode. Because of th
ページ19に含まれる内容の要旨
Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 Table 12 Bass boost settings BASS (dB) BB4 BB3 BB2 BB1 BB0 FLAT SET MIN. SET MAX. SET 00000000 00001000 00010000 00011000 001000 1.1 1.7 001010 1.1 1.7 001100 2.4 3.6 001110 2.4 3.6 010000 3.7 5.4 010010 3.7 5.4 010100 5.2 7.4 010110 5.2 7.4 011000 6.8 9.4 011010 6.8 9.4 011100 8.4 11.3 011110 8.4 11.3 100000 10.2 13.3 100010 10.2 13.3 100100 11.9 15.2 100110 11.9 15.2 101000 13.7 17.3 101010 13.7 17.3 10110
ページ20に含まれる内容の要旨
Philips Semiconductors Preliminary specification Universal Serial Bus (USB) CODEC UDA1325 Filter characteristics playback channel The overall filter characteristic of the UDA1325 in flat mode is given in Fig.4 (de-emphasis off). The overall filter characteristic of the UDA1325 includes the filter characteristics of the DSP in flat mode plus the filter characteristic of the FSDAC (f = 44.1 kHz) s MGM110 - 0 handbook, full pagewidth - 20 volume (dB) - 40 - 60 - 80 - 100 - 120 - 140 - 160 0 10 20 30
