ページ1に含まれる内容の要旨
T TII S Siit ta ar ra a™ ™A AR RM M
M Miic cr ro op pr ro oc ce es ss so or rs s
Yair Hougui
A Ap pp plliic ca at tiio on n E En ng giin ne ee er r
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ページ2に含まれる内容の要旨
TI Embedded Processors Portfolio T TII E Em mb be ed dd de ed d P Pr ro oc ce es ss so or rs s ® Microcontrollers (MCUs) ARM -Based Processors Digital Signal Processors (DSPs) 16-bit ultra- 32-bit 32-bit ARM High- ARM Low-power llo ow w p po ow we er r r re ea all- -t tiim me e C Co or rt te ex x™ ™- -M M3 3 p pe er rf fo or rm ma an nc ce e C Co or rt te ex x- -A A8 8 D DS SP Ps s MCUs MCUs MCUs DSPs MPUs ™ ™ C2000 ™ C6000 Sitara ® Stellaris ™ ™ ® ™ ™ DaVinci ARM Cortex™-A8 Delfino C
ページ3に含まれる内容の要旨
™ What is Sitara ? What’s new Ideal for applications requiring • New platform of high-performance • High-level operating system ARM microprocessors: • 300MHz – 1GHz+ in future devices ® ® ™ ™ • • A Ad dv va an nc ce ed d g gr ra ap ph hiic ca all u us se er r iin nt te er rf fa ac ce es s – – A AR RM M9 9 t to o A AR RM M C Co or rt te ex x - -A A8 8 M MP PU U’’s s • Flexible connectivity and multiple • First new devices: interface options – AM35xx & AM17xx/AM18xx • High system integra
ページ4に含まれる内容の要旨
® ™ Sitara ARM microprocessors A Av va aiilla ab blle e N No ow w IIn n D De ev ve ello op pm me en nt t ARM9 ARM Cortex-A8 ARM Cortex-A8 AM1705 OMAP3503 AM37xx (2Q10) AM1707 OMAP3515 “AM38x Next” (2011) AM1806 AM3505 “AM33x Next” (2011) A AM M1 18 80 08 8 A AM M3 35 51 17 7 Low power ARM9 with Advanced ARM Cortex-A8 Higher Performance Cortex- Integrated peripherals with system integration A8 with enhanced integration • Power efficient (down to 7mW • Up to 1440 DMIPS • Up to 2000 DMIPS s stta
ページ5に含まれる内容の要旨
Develop product designs with TI’s ™ e ex xp pa an nd diin ng g S Siit ta ar ra a M MP PU U p po or rt tf fo olliio o ™ ARM926 Cortex -A8 AM37x Sampling AM35x A AM M1 18 8x x AM17x • High performance general purpose p pr ro oc ce es ss so or r • Advanced graphics/UI • Roadmap to > 1 GHz (>2000 DMIPS) • Power and cost-efficient • Flexible industrial I/O • Up to 450 MHz (495 DMIPS) • • S Stta ar rttiin ng g @ @ $ $5 5 ( (1 1k ku u) ) ® Linux and Windows Embedded CE kernel & drivers Example
ページ6に含まれる内容の要旨
CORTEX-A8 P PR RO OD DU UC CT T D DE ET TA AIIL LS S 6
ページ7に含まれる内容の要旨
AM3517/05 Core and Accelerators Multi window overlay system and resizing for hardware accelerated user interfaces AM3517/05 processors C Co or re es s D Diis sp plla ay y S Su ub bs sy ys st te em m ® ® A AR RM M 600 MHz Cortex A-8 with NEON™ LCD ™ Video 10 bit DAC 3D coprocessor Cortex - Cont- Enc 10 bit DAC Graphics roller PowerVR SGX 3D graphics A8 Accelerator Accelerator – up to 10M (3517) Video 1 16 6- -b biit t V Viid de eo o p
ページ8に含まれる内容の要旨
AM3517/05 Peripherals P Pe er riip ph he er ra alls s CAN – High end controller area network Controller (HECC) AM3517/05 USB 2.0 OTG w/PHY processors R RM MIIII E EM MA AC C c co on nt tr ro olllle er r 1 10 0//1 10 00 0 Display Subsystem ® ARM USB HS host x2 LCD ™ Video 10 bit DAC 3D Cortex - Cont- MMC/SD card interface x3 Enc 10 bit DAC Graphics roller A8 LCD controller and TV out Accelerator ( (3 35 51 17 7) ) V Viid d
ページ9に含まれる内容の要旨
AM3505/17 Platforms 3D Applications Shared Software Graphics Peripheral Compatibility Compatibility Set ™ AM Graphics ARM Open GL ES 2.0 Peripherals AM3517 Cortex-A8 600 MHz ™ AM ARM P Pe er riip ph he er ra alls s A AM M3 35 50 05 5 C Co or rtte ex x- -A A8 8 600 MHz P Piin n- -ffo or r- -p piin n c co om mp pa attiib blle e Availability subject to applicable lead times 9
ページ10に含まれる内容の要旨
CORTEX A-8 : Highlights • First ARMv7 instruction-set architecture • Superscalar architecture delivers high performance – – A Ad dv va an nc ce ed d d dy yn na am miic c B Br ra an nc ch h p pr re ed diic cttiio on n • 256 KB unified L2 cache – – D De ed diic ca atte ed d,, llo ow w- -lla atte en nc cy y,, h hiig gh h- -B BW W iin ntte er rffa ac ce e tto o L L1 1 c ca ac ch he e • Enhanced VFPv3 – Doubles number of double-precision registers – – A Ad dd ds s n ne ew w iin ns sttr ru
ページ11に含まれる内容の要旨
AM35x Memory Controller • Two dedicated memory c co on nttr ro olllle er rs s//o on ne e iin ntte er rn na all memory – SDRAM controller (EMIF4) – – G Ge en ne er ra all p pu ur rp po os se e m me em mo or ry y controller (GPMC) – Internal memory (SRAM) • On Chip Memory [SRAM-64 Kb] • • O Op pe er ra atte es s a att ffu ullll L L3 3 iin ntte er rc co on nn ne ec ctt (64bit@Core Clock /2) 11
ページ12に含まれる内容の要旨
GPMC Controller • 16-bit external memory AM35x controller Supported PsRAM, OneNAND, • • G GP PM MC C c ca an n c co om mm mu un niic ca atte e w wiitth h NOR/NAND Flash, ASYNC Logic many external devices: 1GB (128MB per CS- – External asynchronous/synchronous 8- m mu ux x m mo od de e) ) b biitt w wiid de e m me em mo or ry y//d de ev viic ce e Supported Size (bits) 16 KB (2 KB per CS – External asynchronous/synchronous non-mux 16-bit wide memory/device mode) – – E Ex xtte er rn na
ページ13に含まれる内容の要旨
DDR Controller A AM M3 35 51 17 7//0 05 5 • Supports mDDR / DDR2 mDDR/DDR2 SDRAM • • D DD DR R c co on nttr ro olllle er r h ha as s tth hr re ee e S Su up pp po or rtte ed d functional blocks: 810MB/sec Measured – Virtual Rotated Frame Buffer Throughput (VRFB), supporting rotations of 0 0 ,, 9 90 0 ,, 1 18 80 0 ,,2 27 70 0 16M, 32M (2 Supported Banks) – SDRAM memory-access Size (bits) scheduler (SMS) 6 64 4M M,, 1 12 28 8M M,, 2 25 56 6M M,, • • O Op pttiim miiz ze es s lla
ページ14に含まれる内容の要旨
Power Management • • A AM M3 35 5x x p po ow we er r m ma an na ag ge em me en ntt ffe ea attu ur re es s:: – Single voltage and power domain – Multiple clock domains – – S Siin ng glle e O Op pe er ra attiin ng g V Vo olltta ag ge e a an nd d F Fr re eq qu ue en nc cy y – Low power mode (standby) • • P Po ow we er r,, R Re es se ett a an nd d C Cllo oc ck k M Ma an na ag ge em me en ntt ( (P PR RC CM M) ) m mo od du ulle e c co on nttr ro olls s p po ow we er r m ma an na ag ge
ページ15に含まれる内容の要旨
AM35x Power Options T TP PS S6 65 50 07 73 32 2 Touchscreen Interface TPS65910 1 10 0- -b biitt A AD DC C 4 inputs IIn ntte eg gr ra atte ed d AC & USB RTC 32kHz B Ba atttte er ry y C Ch ha ar rg ge er r w/ DPPM 10mA LED 25mA wLED D Dr riiv ve er rs s Driver Driver TPS65023 3 DCDC 3 DCDC 3 DCDC P Po ow we er r 1x 5V Boost 2 2 L LD DO O 2 2 L LD DO O 9 9 L LD DO O II2 2C C 2 HS I2C 1 I2C 1 I2C IIn ntte er rffa ac ce e 15 IIn ntte eg gr ra attiio on n
ページ16に含まれる内容の要旨
AM35x development tools AM3517 AM3517 eXperimenter evaluation module $995 $199 • Includes Module and • AM3517 interface board found on • PowerVR SGX AM3517EVM • Integrated processor, power a an nd d W Wiiffii m mo od du ulle e • • T To ou uc ch h s sc cr re ee en n L LC CD D • Touch screen LCD available for purchase • CAN, JTAG, Ethernet and separately more via applications board • Available only through • Modular design L Lo og giic cP PD D ® ® • • L Liin nu ux x a an nd d W Wi
ページ17に含まれる内容の要旨
Getting Help • TI E2E forums – http://e2e.ti.com • Embedded Processor Wiki page: – http://wiki.omap.com/index.php/Main_Page • • S Se ellff S Se er rv ve e C Co olllla atte er ra all – http://ap-fpdsp- swapps.dal.design.ti.com/index.php/Self_serve_collateral • OMAP Developer Series Videos (5 Parts) – http://focus.ti.com/docs/prod/folders/print/omap3530.html ( (o or r o on n Y Yo ou uT Tu ub be e) ) • Online Training www.ti.com/onlinetraining 17
ページ18に含まれる内容の要旨
ARM-9 P PR RO OD DU UC CT T D DE ET TA AIIL LS S 18
ページ19に含まれる内容の要旨
Multiple peripheral, memory and performance combinations A AM M1 18 80 06 6 A AM M1 18 80 08 8 A AM M1 17 70 05 5 A AM M1 17 70 07 7 ® ® O OS S & & T TII- -p pr ro ov viid de ed d L Liin nu ux x & & W Wiin nd do ow ws s E Em mb be ed dd de ed d C CE E plus Developer Network offerings drivers Example PRU UART, PRU CAN, touch screen interface demos, etc code 375 and 450 MHz ARM9 Memory DDR2/mDDR/ DDR2/mDDR/ SDRAM SDRAM interface SDRAM SDRAM USB 2.0 PRU PRU USB 2.0 PRU USB 2.0 PRU USB 2.
ページ20に含まれる内容の要旨
AM1808/1806 microprocessors F Fe ea at tu ur re es s CPU Cores The boxes with yellow border are features found in AM1808 and not in AM1806 – ARM926EJ-S™ (MPU) up to 450 MHz ARM9 1024x1024 High Speed Memory Subsystem L LC CD D L LC CD D A AD DC C F FP PG GA A,, o or r – – A AR RM M: : C Co on nt tr ro olllle er r DSP Interface – 16KB – L1 Program Cache – 16KB – L1 Data Cache ARM uPP – On-chip 128KB RAM – mDDR, DDR2, SDRAM 926EJ-S C CP PU U 1 12 28 8K KB B V Viid de eo o P PR RU U
