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TM
PowerPC Applications
IBM25CPC710 Bridge Chip:
IBM Microelectronics
Enhancements and Changes in the
Research Triangle Park, NC
ppcsupp@us.ibm.com
DD3.x revisions
http://www.chips.ibm.com
November 8, 2001 Version 1.0
Abstract
This Application Note describes the differences between the CPC710-100+ (DD2) and the
CPC710 (DD3.x) versions of the PowerPC Dual PCI/Memory Controller companion chip. The
purpose of this note is to provide designers with an overview of the changes a
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Processor Interface: v Voltage Level and Bus Speed Differences Ø The CPC710 DD3.x revision supports 60x bus operation at speeds of up to 133MHz, at an I/O voltage of 2.5V. This interface voltage level is supported on the PPC750L, 750CX, and 750CXe processors. This is a change from the previous revision. v I/O Signal New Functionality Ø Set bit 18 of 60x Bus Arbiter register (system register CPC0_ABCNTL) to 1 to allow the signal level of SYS_TA_ to be confirmed and held at a high l
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Memory Interface: v Extended SDRAM Addressing Ø The signal MADDR13 has been added to support the following additional SDRAM organizations: § 13-12-2, 14-9-2, 14-10-2, 14-11-2, 14-12-2 § Register SDRAM0_MCER [26:29] is used to select the SDRAM organization; refer to the CPC710-133 User’s Manual for more information. v Extended Memory Size Ø The Memory controller has been modified to support up to six banks of dual DIMM interleaved 72-bit memory, for a total memory addressing range
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v Extended Addressing of PCI Memory Ø System memory addressing range increased from 2GB to 4GB. The standard addressing capability is 2GB; with the size defined by bits 24-31 of PCI local registers PCILx_PSSIZE. The address extension is implemented by setting bit 27 of chip control register CPC0_PGCHP. In this case, the FINE option for selection of less than1MB granularity (enabled in CPC710-100+ dd2 in the memory write protection register SDRAM0_MWPR) is not available. PCI In
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plane. In most circumstances, however, it is prudent to place a filter circuit on AVDD; refer to the CPC710 DD3.x User’s Manual for more information. Ø The PLL is now set up and controlled by external signals PLL_RANGE [1:0] and 6 external signals PLL_TUNE [5:0] instead of PLL133 and PLL_TUNE [1:0]. This is a change from the previous revision. Packaging Changes: v FC-PBGA Package instead of CBGA Ø The CPC710 DD3.x is offered in a 35mm 728 pin FC-PBGA (Flip Chip Plastic Ball Grid A
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v I/O Pin Additions: The following I/Os are new on the DD3 revision: INTERFACE SIGNAL NAME IMPACT 60x bus Interface SYS_BG2_, SYS_BG3_, SYS_MCP2, New for 4-way CPU support SYS_MCP3, SYS_HRESET2, SYS_HRESET3, SYS_SRESET2, SYS_SRESET3 60x bus Interface SYS_TA_HIT Memory Interface MADDR13 Used for newer memory sizes Clock Inputs PLL_RANGE0, PLL_RANGE1, New; used for setup and control PLL_TUNE2, PLL_TUNE3, PLL_TUNE4, of PLL PLL_TUNE5 v I/O Pins Multiplexed: The following I/Os a
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Performance Enhancements and Improvements: v The CPC710 DD3.x revision has improvements to support PCI Long Burst Write operations and improvements in the deadlock prevention circuits. These enhancements can be selected by programming select bits in PCI local registers PCILx_PSWCR and PCILx_DLKCTRL. Ø Crossing a 4K boundary during burst operations results in a stop on the PCI bus. By default operation, snooping is done on the current PCI master’s address. A new option is provided to al
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(c) Copyright International Business Machines Corporation 2001 All Rights Reserved Printed in the United States of America November 2001 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both: IBM PowerPC IBM Logo Other company, product and service names may be trademarks or service marks of others. All information contained in this document is subject to change without notice. T
