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®
Int e l 41 3808 a nd 41 3812 I / O
Controll er s inTPER Mode
eluals Ma Devoper’n
Octber o 2007
US 05-001 Order Number: 3178
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ITI T I DOCUMENT IPSINFORMAHONN WITSNNECTITCPRDIP OR L IRROVIDEDI N OONHNEL® OMPLIED, BY ESTOUCTPENO LICENSE, EXPRESS O S. NDI OTI R ON E VI ON T GIYINTELLECTUTT HSANS O T O TI NGLAR E ARRT YAN X D ISC TS O LI ABILI ASSU F O ADFI NNTEL PRODUC SALE /OR USE O TS INCLUTO DINGLI TARTIF ABILIA TESS FOR A PCUING TO I WRRANTITYOR SE, LAR PURN ES RELA PO ied are not ntend e I.loducts nt pr R, COPYRT OPR INTELLECTURTYPRHERIGT OEAL OHGI TH TENT FA, OR I RINGMENT OF ANY PN E ABI MERCHANTLITY for i
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® Conte t n s —Intel 812 08 and 413 138 4 t 1. 0 Intro du ction ............................................................................................................... 3 6 1.1 Design-in Consid erations .................................................................................... 38 1.1. 1 Softw are ............................................................................................... 39 1.2 Documen tation Referen ce s ......................................................
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® Intel 12—Contents 8 and 4138 1380 4 2. 2.6 Internal Bus Op eratio n . ........................................................................... 77 2. 3 B ig Endian Byte Swapp in g................................................................................... 78 2. 3.1 Inbound Byte Swappi ng ........................................................................... 78 2. 3.2 O utbound Byte Swapping......................................................................... 79 2. 4 C om pa c
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® Conte t n s —Intel 812 08 and 413 138 4 2.7.. 51 M ase tr Abors t fo r Outbound Rea d or Write Req ue st ..................... 109 2.7. . 5 2 I n b o u n d Read Co mp letio n o n r I b o u n d Co n fig ura i t o n Wri e t Co mp letio n M e s s a ge110 2.7.. 53 M ase tr-Aborts Sign al ed by th e ATU as a Ta rget ........................... 110 2.7.5.3.1 Uncorrectable Address Errors ...........................................110 2.7.5.3.2 Internal Bus Master-Abort ...............................
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® Intel 12—Contents 8 and 4138 1380 4 2. 14.8 A TU Cla s s Co de Regis t er - A T U CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 2. 14.9 A TU Cac h e lin e Si ze Regi ster - ATU CLSR .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 2. 14.10 ATU Laten cy Timer Reg iste r - AT ULT . ...................................................... 152 2. 14.11 A T U Hea der T y
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® Conte t n s —Intel 812 08 and 413 138 4 2.14.63 HSCNT _RL- Ho-Swa t p Co ntro l/Status Reg iste r . .. ..................................... 202 2.14.64 Inb o u n d A T U Ba se Ad dres s Regis t er 3 - IA BA R3 .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 2.14.65 Inbound ATU Upper Base Address Reg ise tr 3 - IAUBAR3 ............................ 205 2.14.66 Inbound ATUi Lmit Re gister 3 - IAR3 L ..................................................... 206 2.14.67
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® Intel 12—Contents 8 and 4138 1380 4 3. 3.5. 1 Outbo und Co nfiguration Cyc le Erro r Conditions............................ 253 3. 3.5. 2 O u t bo un d Co nfi g u r atio n Co mp letio n s w i th Retry S t atu s (CRS ) . . . . . . . 253 3. 3.5. 3 Outbo und PCI Express Mess ag e Transactions .............................. 254 3. 3.5. 4 Compl etio n Time ou t Mechanism ................................................ 254 3. 4 B ig Endian Byte Swapp in g............................................
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® Conte t n s —Intel 812 08 and 413 138 4 3.17.5 ATU Co mm an d Regis t er - A T U C MD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 3.17.6 ATU Status Reg ise tr - ATUS R . ................................................................ 299 3.17.7 ATU Rev ision ID Reg iste r - ATURID ......................................................... 300 3.17.8 ATU Class Co de Reg ister - ATU CCR ....................................
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® Intel 12—Contents 8 and 4138 1380 4 3. 17.60 PCI Express Device Status Re gister - PE_DS TS ......................................... 346 3. 17.61 P C I E xpre s s Lin k Ca pab ili i t es Regi ster - P E C _ L AP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 3. 17.62 P C I E xpre s s Lin k Co n ro t l Re gis t er - P E LCTL _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 3. 17.63 P C I E xpre s s Lin k S a t t us R
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® Conte t n s —Intel 812 08 and 413 138 4 3.17.111Ou t bo u n d Ve n d o r Me ss age Hea d e r Regi ster 1 - OV MHR1 . . . . . . . . . . . . . . . . . . . . . . . . . . 389 3.17.112Ou t bo u n d Ve n d o r Me ss age Hea d e r Regi ster 2 - OV MHR2 . . . . . . . . . . . . . . . . . . . . . . . . . . 390 3.17.113Ou t bo u n d Ve n d o r Me ss age Hea d e r Regi ster 3 - OV MHR3 . . . . . . . . . . . . . . . . . . . . . . . . . . 390 3.17.114Ou t bo u n d Ve n d o r Me ss age P ayl oa d Re gis e t
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® Intel 12—Contents 8 and 4138 1380 4 4. 7.26 M S - X I Ca pa bil i ty Iden tifi er Reg iste r - MS I-X_Ca p_ID . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 4. 7.27 M S - X I Ne t e xt I m P o i n ter Regi ster - MS - X I _ Next_Item_P r t . . .. . .. . .. .. . .. . .. .. . .. . .. 436 4. 7.28 MSI-X Message Contro l Reg iste r- MS I-X_M CR .......................................... 437 4. 7.29 M S - X I Ta ble Of fse t Regis t er — MS I-X_Ta ble _ Offs et .. . . . . . . .
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® Conte t n s —Intel 812 08 and 413 138 4 7.1 Ove rview . ...................................................................................................... 485 7.2 Theory of Operation . .. ...................................................................................... 486 7.2. 1 System Co ntro lle r ................................................................................ 486 7.2. 2 Internal Bus Req ue sterDs I . ................................................................
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® Intel 12—Contents 8 and 4138 1380 4 8. 3.3 E rro r Co rrection and Detectio n . .............................................................. 519 8. 3.3. 1 ECC Genera tion....................................................................... 520 8. 3.3. 2 ECC Genera tion for Paiartl Writes .............................................. 521 8. 3.3. 3 ECC Ch ec king ......................................................................... 522 8. 3.3. 4 Scrubbi ng ..............................
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® Conte t n s —Intel 812 08 and 413 138 4 .110 Overview ....................................................................................................... 565 .210 Th eo ry of Operation . .. ...................................................................................... 566 .210.1 Interru pt Controller Unit ........................................................................ 566 ® . 10 3 Th e In e t l X S c a l e Proc es so r Exce ptions Arch itec ture ...........................
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® Intel 12—Contents 8 and 4138 1380 4 10. 7.26 In terru pt Prio rity Reg ister 1— IP R1 .. ...................................................... 620 10. 7.27 In terru pt Prio rity Reg ister 2— IP R2 .. ...................................................... 621 10. 7.28 In terru pt Prio rity Reg ister 3— IP R3 .. ...................................................... 622 10. 7.29 In terru pt Prio rity Reg ister 4— IP R4 .. ...................................................... 623 10. 7.30 In te
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® Conte t n s —Intel 812 08 and 413 138 4 . 12 4 .6 SM B u s Co n ro t ll er A R D D 0 Regis t er Nu mb er — SM _ADDR0 . . . . . . . . . . . . . . . . . . . . . . . . . . 657 .412.7 SM Bus Contro ll er Daa t Reg ister — SM_DATA ............................................ 658 .412.8 SM Bus Contro ll er Status Reg ise tr — SM_S TS ........................................... 658 13.0 UARTs .............................................................................................................
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® Intel 12—Contents 8 and 4138 1380 4 14. 4 S la ve Mode Progra mm in g Exam ples .. ................................................................. 708 14. 4.1 Initializ e Unit ....................................................................................... 708 14. 4.2 Wrie t 1 Byte as a Slav e ......................................................................... 708 14. 4.3 Read 2 Bye ts as a Slave ........................................................................ 708 14. 5
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® Conte t n s —Intel 812 08 and 413 138 4 .516.7.3 Th reshold Even ts .................................................................... 758 .516.7.4 PCI Interf ac e Even ts ............................................................... 759 .516.7.5 PCI Ex pres s In terface Ev ens t .................................................... 760 .516.7.6 No rth In tern al Bus Ev ens t ........................................................ 761 .516.7.7 South Internal Bus Even ts ...................
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® Intel 12—Contents 8 and 4138 1380 4 18.E 2.2.5xit2-IR Stat1e ......................................................................... 789 18.U 2.2.6pda 1te-IR State ...................................................................... 789 18. 2.3 T AP Co ntro lle r Reg isters ........................................................................ 790 18. 2.3. 1 Ins truction Re gister ................................................................. 790 18. 2.3. 2 Ins tructions .............
