ページ1に含まれる内容の要旨
FS781/82/84
Low EMI Spectrum Spread Clock
Features Functional Description
The Cypress FS781/82/84 are Spread Spectrum clock
• Spread Spectrum clock generator (SSCG) with 1×, 2×,
generator ICs (SSCG) designed for the purpose of reducing
and 4× outputs
electromagnetic interference (EMI) found in today’s
• 6- to 82-MHz operating frequency range
high-speed digital systems.
• Modulates external clocks including crystals, crystal
The FS781/82/84 SSCG clocks use a Cypress-proprietary
oscillators
ページ2に含まれる内容の要旨
FS781/82/84 Pin Configuration Block Diagram Loop Filter 4(6) Xin 1 8 VDD 250 K Xout 2 7 S0 FS78x S1 3 6 FSOUT Reference 1(3) Xin Divider Phase 8 pF LF 4 5 VSS Detector VCO 10 pF. 8 Pin SOIC Package Modulation Control 2(4) Xout 8 pF VCO / N S0 1 8 FSOUT Output VDD 2 7 VSS FS78x Divider Power Contol 8(2) VDD Input Control Logic 6(8) VDD FSOUT and Logic Xin 3 6 LF Mux Xout 4 5 S1 VSS (TSSOP Pin #) 5(7) 3(5) 7(1) 8 Pin TSSOP Package VSS S1 S0 Pin Description Pin Name I/O Type Description 1/2 (SOIC
ページ3に含まれる内容の要旨
FS781/82/84 [1, 2, 3, 4] Table 2. FS781/82/84 Recommended Loop Filter Values C7 (pF) @ +3.3 VDC ±5% (R6 = 3.3K) [3] [3] [3] [3] [3] [3] [3] Input MHz S1 S0 BW = 1.0% BW = 1.5% BW = 2.0% BW = 2.5% BW = 3.0% BW = 3.5% BW = 4.0% 6 0 0 10,000/1000 1550 910 780 700 640 560 8 0 0 10,000/330 990 820 640 520 450 400 10 0 0 1040 680 460 360 300 240 210 12 0 0 830 420 300 220 200 190 170 14 0 0 580 230 200 160 140 100 80 16 0 1 10000 980 760 580 470 410 385 18 0 1 1200 750 580 470 415 370 300 20 0 1 10
ページ4に含まれる内容の要旨
FS781/82/84 [1, 2, 3, 4] Table 3. FS781/82/84 Recommended Loop Filter Values C7 (pF) @ +5.0 VDC ±5% (R6 = 3.3K) [3] [3] [3] [3] [3] [3] [3] Input MHz S1 S0 BW = 1.0% BW = 1.5% BW = 2.0% BW = 2.5% BW = 3.0% BW = 3.5% BW = 4.0% 6 0 0 1140 1030 930 830 710 610 510 8 0 0 1170 970 740 570 460 400 280 10 0 0 1030 660 430 350 280 210 130 12 0 0 760 340 230 200 180 160 130 14 0 0 450 240 180 140 100 70 50 16 0 1 2490 970 730 590 480 430 370 18 0 1 2490 870 650 510 430 370 310 20 0 1 1360 680 480 370
ページ5に含まれる内容の要旨
FS781/82/84 Table 4. Modulation Rate Divider Ratios S1 S0 Input Frequency Range (MHz) Modulation Divider Number 0 0 6 to 16 120 0 1 16 to 32 240 1 0 32 to 66 480 1 1 66 to 82 720 quently, higher energy peaks. Regulatory agencies test SSCG Modulation Profile electronic equipment by the amount of peak energy radiated The digital control inputs S0 and S1 determine the modulation from the equipment. By reducing the peak energy at the funda- frequency of FS781/2/4 products. The input frequency is m
ページ6に含まれる内容の要旨
FS781/82/84 50% 50% Tc = 50 ns. Figure 2. 20-MHz Unmodulated Clock From the above parameters, the output clock at FSOUT will be sweeping symmetrically around a center frequency of 20 MHz. Tc =49.50 ns. Tc = 50.50 n The minimum and maximum extremes of this clock will be +200 kHz and –200 kHz. So we have a clock that is sweeping Figure 4. Period Comparison Chart from 19.8 MHz to 20.2 MHz and back again. If we were to look at this clock on a spectrum analyzer we would see the picture Looking at F
ページ7に含まれる内容の要旨
FS781/82/84 Crystal is 20 MHz is 1st Order with 18 pF load capacitance. C2 1 8 VDD Xin VDD C1 20 MHz If Crystal load capacitance is 0.1 uF 27 pF Y1 different than 18 pF, C1 and C2 must be re-calculated. C3 2 7 Xout S0 For third overtone crystals, a FS781 27 pF parallel or series resonant trap (SOIC) is required. 3 6 FSOUT S1 FSOUT 4 5 Mount loop filter components as LF VSS close to LF pin as possible. R6 C7 C8 ** ** Occasionally, C8 is used to create a se
ページ8に含まれる内容の要旨
FS781/82/84 [6] Absolute Maximum Ratings This device contains circuitry to protect the input against this circuit. For proper operation, V and V should be IN OUT damage due to high static voltages or electric fields; however, constrained to the range, V < (V or V ) < V . All digital SS IN OUT DD precautions should be taken to avoid application of any inputs are tied high or low internally. Refers to electrical speci- voltage higher than the absolute maximum rated voltages to fications for oper
ページ9に含まれる内容の要旨
FS781/82/84 Table 7. Timing Electrical Characteristics V = 3.3V and 5.0V ±10%, T = 0°C to 70°C, C = 15 pF, X = 48 MHz (continued) DD A L IN Parameter Description Min. Typ. Max. Unit CCJ FSOUT, Cycle-to-Cycle Jitter, 48 MHz @ 3.30 VDC (Pin 6) – 320 370 ps CCJ FSOUT, Cycle-to-Cycle Jitter, 48 MHz @ 5.0 VDC (Pin 6) – 310 360 ps CCJ FSOUT, Cycle-to-Cycle Jitter, 72 MHz @ 3.30 VDC (Pin 6) – 270 325 ps CCJ FSOUT, Cycle-to-Cycle Jitter, 72 MHz @ 5.0 VDC (Pin 6) – 390 440 ps Table 8. Range Selectio
ページ10に含まれる内容の要旨
FS781/82/84 Marking Example Cypress Cypress FS781BS FS781BT Date Code, Lot # Date Code, Lot # FS781 B S Package S = SOIC T = TSSOP Revision Cypress Device Driver Package Drawing and Dimensions 8 Lead (150 Mil) SOIC S08 8-lead (150-Mil) SOIC S8 PIN1ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN1IDISOPTIONAL, ROUND ON SINGLE LEADFRAME 0.150[3.810] RECTANGULAR ON MATRIX LEADFRAME 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 4. PACKAGE WEIGHT 0.07gms 0.244[6.197] PART # S08.15 STANDARD
ページ11に含まれる内容の要旨
FS781/82/84 Package Drawing and Dimensions (continued) 8-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z8 PIN1ID 1 DIMENSIONS IN MM[INCHES] MIN. MAX. 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] 8 0.65[0.025] BSC. 0.25[0.010] 0.19[0.007] 1.10[0.043] MAX. 0.30[0.012] BSC GAUGE 0°-8° PLANE 0.076[0.003] 0.85[0.033] 0.95[0.037] 0.50[0.020] 0.05[0.002] 0.09[[0.003] SEATING 0.15[0.006] 0.70[0.027] PLANE 0.20[0.008] 2.90[0.114] 3.10[0.122] 51-85093-*A All product and company names mentione
ページ12に含まれる内容の要旨
FS781/82/84 Document History Page Document Title: FS781/82/84 Low EMI Spectrum Spread Clock Document Number: 38-07029 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 106948 06/07/01 IKA Convert from IMI to Cypress *A 111654 02/27/02 IKL Add new marking suffix for SOIC packages. Converted to FrameMaker. *B 118355 08/30/02 RGL Swap the location of S0 and S1 in tables 2 and 3 in pages 2,3 and 4. *C 122679 12/14/02 RBI Add power up requirements to operating conditions informati
