ページ1に含まれる内容の要旨
MQ162-03
Application Manual
Real Time Clock Module
RTC-72421/72423
Model Product Number
RTC-72421 A Q4272421x000100
RTC-72421 B Q4272421x000200
RTC-72423 A Q4272423x000600
RTC-72423 Q4272423x000700
ページ2に含まれる内容の要旨
In pursuit of "Saving" Technology ,Epson electronic device. Our Lineup of semiconductors, Liquid crystal displays and quartz devices assists in creating the products of our customers' dreams. Epson IS energy savings. NOTICE • The material is subject to change without notice. • Any part of this material may not be reproduced or duplicated in any form or any means
ページ3に含まれる内容の要旨
RTC - 72421 / 72423 CONTENTS Overview............................................................................................. 1 Block diagram ..................................................................................... 1 Terminal connections.......................................................................... 2 Terminal functions............................................................................... 3 Characteristics ...............................
ページ4に含まれる内容の要旨
RTC - 72421 / 72423 4-BIT PARALLEL INTERFACE REAL TIME CLOCK MODULE RTC - 72421 / 72423 • Built-in crystal unit removes need for adjustment and reduces installation costs • Microprocessor bus compatible ( tWW, tRD = 120 ns ) DD • Use of C-MOS IC enables low current consumption ( 5 µ A Max., at V = 2.0 V ) • Compatibility with Intel CPU bus • Address latch enable (ALE) pin compatible with multiplex bus CPUs • Time (hours, minutes, seconds) and calendar (year, month, day) counter •
ページ5に含まれる内容の要旨
RTC - 72421 / 72423 Terminal connections RTC-72421 RTC-72423 STD.P 1 24 VDD STD.P 1 18 VDD () CS 0 2 23 VDD () CS0 2 17 VDD () N.C. 3 22 VDD ALE 4 21 N.C. ( ) ALE 3 16 VDD A 0 5 20 CS1 A0 4 15 CS1 N.C. 6 19 D0 1 A 7 18 N.C. A1 5 14 D0 N.C. 8 17 N.C. A2 6 13 D1 A 2 9 16 D1 3 2 A 10 15 D A3 7 12 D2 RD 11 14 D3 GND 12 13 WR RD 8 11 D3 GND 9 10 WR The (VDD) pins are at the same electrical level as VDD. Do not connect these pins externally. The N.C. pins are not connected internal
ページ6に含まれる内容の要旨
RTC - 72421 / 72423 Terminal functions Pin No. Input/ou Function Signal tput RTC-72421 RTC-72423 Connect these pines to a bi-directional data bus or CPU data bus. Use this bus to read to and write from the internal counter and registers. CS1 CS0 RD WR Mode of D0 to D3 H L L H Output mode (read mode) D0-D3 Bi- 11−14 14−16, 19 H L H L Input mode (write mode) (Data bus) direction H L L L Do not use L H or L High impedance (back-up mode) H H H or L High impedance (RTC not select
ページ7に含まれる内容の要旨
RTC - 72421 / 72423 Characteristics 1. Absolute maximum ratings Item Symbol Condition Specification Unit Supply voltage VDD Ta=+25 °C −0.3 to 7.0 V Input voltage VI Ta=+25 °C GND−0.3 to VDD+0.3 V Output voltage VO ° − V Ta=+25 C GND 0.3 to VDD+0.3 RTC-72421 −55 to +85 °C Storage temperature TSTG RTC-72423 −55 to +125 °C 2. Recommended operating conditions Item Symbol Condition Specification Unit Supply voltage VDD 4.5 to 5.5 V RTC-72421 ; −10 to +70 °C Op
ページ8に含まれる内容の要旨
RTC - 72421 / 72423 Switching characteristics (AC characteristics) 1. When ALE is used Write mode ( VDD=5 V ± 0.5 V, RTC-72421;Ta=−10 °C to +70 °C, RTC-72423;Ta=−40 °C to +85 °C ) Item Symbol Condition Min. Max. Unit CS1 set-up time tSU(CS1) 1000 Address set-up time before ALE tSU(A-ALE) 50 Address hold time after ALE th(ALE-A) 50 ALE pulse width tw(ALE) 80 ALE set-up time before write tSU(ALE-W) 0 Write pulse width tw(W) 120 ns ALE set-up time after
ページ9に含まれる内容の要旨
RTC - 72421 / 72423 2. When ALE is fixed at VDD Write mode ( VDD=5 V ± 0.5 V, RTC-72421;Ta=−10 °C to +70 °C, RTC-72423;Ta=−40 °C to +85 °C ) Item Symbol Condition Min. Max. Unit CS1 set-up time tSU(CS1) 1000 CS1 hold time th(CS1) 1000 Address set-up time before write tSU(A-W) 50 Address hold time after write th(W-A) 10 ns Write pulse width tw(W) 120 Data input set-up time before write tSU(D-W) 80 Data input hold time after write th(W-D) 10 Write reco
ページ10に含まれる内容の要旨
RTC - 72421 / 72423 Registers 1. Register table Address Register Data Count A3 A2 A1 A0 Remarks (Hex) name (BCD) D3 D2 D1 D0 0 0 0 0 0 S1 s8 s4 s2 s1 0 to 9 1-second digit register 1 0 0 0 1 S10 * s40 s20 s10 0 to 5 10-seconds digit register 2 0 0 1 0 MI1 mi8 mi4 mi2 mi1 0 to 9 1-minute digit register 3 0 0 1 1 MI10 * mi40 mi20 mi10 0 to 5 10-minute digit register 4 0 1 0 0 H1 h8 h4 h2 h1 0 to 9 1-hour digit register 5 0 1 0 1 H10 * PM/AM h20 h10 0 to1 or 2 10-hours digit regi
ページ11に含まれる内容の要旨
RTC - 72421 / 72423 4. Setting the fixed-period pulse output mode and fixed-period interrupt mode Mode MASK ITRPT/STND ITRPT/STND STD.P pin Setting of fixed-period output timing Fixed-period pulse output mode 0 0 Set to 1 when Set low when t1 bit 0 0 1 1 active active Fixed-period interrupt mode 0 1 t0 bit 0 1 0 1 Fixed-period pulse output 1 0 or 1 "0" Open-circuit Output period 1/64 s 1 s 1 min. 1 hour inhibited 5. Resetting the fixed-period pulse output mode and fixed-per
ページ12に含まれる内容の要旨
RTC - 72421 / 72423 Register description 1. Timing registers (1) S1 to Y10 registers These registers are 4-bit, positive logic registers in which the digits of the year, month, day, hour, minute, and second are continuously written in BCD code. For example, when(1, 0, 0, 1) has been written to the bits of the S1 register, the current value in the S1 register is 9. As described previously, data is handled by 4-bit BCD codes. Therefore, the S1 to Y10 registers consist of units regi
ページ13に含まれる内容の要旨
RTC - 72421 / 72423 2. CD register (control register D) (1) HOLD bit (D0) Use the HOLD bit when accessing the S1 and W registers. For details, see "Read/write of S1 to W registers". HOLD bit Function HOLD bit 0 The BUSY bit is always 1 (the BUSY status cannot be checked). 1 The BUSY status can be checked. When the HOLD bits is 1 and the BUSY bit is 0, read and write are enabled. When the HOLD bit is 1, any incrementation in the count is held within the RTC. The held incrementation
ページ14に含まれる内容の要旨
RTC - 72421 / 72423 *STD.P pin output IRQ FLAG bit 01 0 1 Interrupt generation (in synchronization with count incrementation) Writing of 0 IRQ FLAG bit. The output levels of the STD.P pin are low (down) and open circuit (up). Note: If the STD.P pin output remains low as set, subsequently generated interrupts are ignored. In order to prevent interrupts from being overlooked, write 0 to the IRQ FLAG bit before the next interrupt is generated, to return the STD.P pin to high. iii.
ページ15に含まれる内容の要旨
RTC - 72421 / 72423 2.Fixed-period interrupt mode (ITRPT/STND=1) 0 1 0 1 MASK bit 0 1 0 IRQ FLAG bit Nothing is output because the MASK bit is at 1 *STD. P pin Interrupt timing Reset at the point at which 0 is written to the IRF FLAG bit No interrupts are generated while the MASK bit is at 1 The output levels of the STD.P pin are low(down) and open circuit(up). (2) ITRPT/STND bit (D1) The ITRPT/STND bit specifies fixed-period pulse output mode or fixed-period inte
ページ16に含まれる内容の要旨
RTC - 72421 / 72423 4. CF register (control register F) (1) RESET bit (D0) Writing 1 to the RESET bit clears the sub-second bits of the internal counter down to the 1/256-seconds counter. The reset continues for as long as the RESET bit is 1. End the reset by writing 0 to the RESET bit. If the level of the CS1 pin goes low, the RESET bit is automatically cleared to 0. (2) STOP bit (D1) Writing 1 to the STOP bit stops the clock of the internal counter from the 1/8192 second bit onw
ページ17に含まれる内容の要旨
RTC - 72421 / 72423 Using the RTC-72421/RTC-72423 1. Power-on procedure (initialization) When power is turned on, the contents of all registers and the output from the STD.P pin are undefined. Therefore, all the registers must be initialized after power on. Follow the procedure given below for initialization. Power On Start the counter At ths point, there is no need to (A) Initialize the control registers check the BUSY bit. Check the status of the BUSY bit (B) STOP and RESET the
ページ18に含まれる内容の要旨
RTC - 72421 / 72423 (A)Starting the count START Set the CF register Reg.F ← 0*00B ← TEST 0 ← 24/12 0 or 1 ← STOP 0 ← RESET 0 Set the CE register This setting is not necessary when the STD.P pin is not used Set the CD register Reg.D ← 0*00B ← 30 s ADJ 0 Set the IRQ FLAG bit to 0 when fixed-period ← IRQ FLAG 0 or 1 ← interrupt mode is used, or to 1when it is not HOLD 0 used. To next process (B) Checking the status of the BUSY bit START HOLD bit ← 1 Read the BUSY bit NO BUSY bit=
ページ19に含まれる内容の要旨
RTC - 72421 / 72423 2. Read/write of S1 to W registers Use one of the procedures shown below to access registers other than the control registers (CD, CE, and CF) while the RTC is operating. Note that the control registers can be accessed regardless of the status of the BUSY bit. Read or write when the HOLD bit is used From previous process From previous process HOLD bit ← 1 HOLD bit ← 1 Read the BUSY bit Read the BUSY bit NO or NO BUSY bit = 0? BUSY bit = 0? YES
ページ20に含まれる内容の要旨
RTC - 72421 / 72423 4. Using the CS1 pin The RTC-72421/RTC-72423 has 2 chip-select signal systems: CS0 and CS1. Use CS0 as chip-select for ordinary bus access. CS1 is not only used for CPU bus control, it also has the main function of switching between standby mode and operating mode. (1) Functions Providing the CS1 pin with the rated voltage levels enables CS1 to have the following functions: • Enabling interface with microprocessor during operation within the operating voltage
