ページ1に含まれる内容の要旨
Video Coprocessor
CYV15G0104TRB
Independent Clock HOTLink II™ Serializer and
Reclocking Deserializer
transfer of data over a variety of high-speed serial links
Features
including SMPTE 292M and SMPTE 259M video applications.
®
• Second-generation HOTLink technology It supports signaling rates in the range of 195 to 1500 Mbps
per serial link. The transmit and receive channels are
• Compliant to SMPTE 292M and SMPTE 259M video
independent and can operate simultaneously at different
standards
rate
ページ2に含まれる内容の要旨
CYV15G0104TRB The CYV15G0104TRB is ideal for SMPTE applications where format routers, switchers, format converters, SDI monitors, different data rates and serial interface standards are cameras, and camera control units. necessary for each channel. Some applications include multi- CYV15G0104TRB Serializer and Reclocking Deserializer Logic Block Diagram x10 x10 Phase Align Deserializer Buffer Serializer RX TX Reclocker Document #: 38-02100 Rev. *B Page 2 of 27 [+] Feedback ROUTA1± ROUTA2± RXDA[
ページ3に含まれる内容の要旨
CYV15G0104TRB Reclocking Deserializer Path Block Diagram RESET TRST JTAG TRGRATEA TMS Boundary TCLK x2 TRGCLKA Scan TDI Controller TDO SDASEL[2..1]A[1:0] LDTDEN LFIA Receive Signal INSELA Monitor 10 RXDA[9:0] 10 10 INA1+ INA1– Clock & BISTSTA INA2+ Data INA2– Recovery RXCLKA+ PLL ÷2 ULCA RXCLKA– SPDSELA RXBISTA[1:0] RXPLLPDA RXRATEA Recovered Serial Data Recovered Character Clock ROE[2..1]A ROUTA1+ Reclocker ROE[2..1]A ROUTA1– Output PLL Clock Multiplier ROUTA2+ ROUTA2– RECLKOA Character-Rate
ページ4に含まれる内容の要旨
CYV15G0104TRB [1] Pin Configuration (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A TOUT TOUT IN ROUT IN ROUT NC NC NC NC V NC GND GND GND V V NC V NC CC CC CC CC B1– B2– A1– A1– A2– A2– B TOUT TOUT IN ROUT IN ROUT V NC V NC V V GND NC GND V NC NC NC NC CC CC CC CC CC B1+ B2+ A1+ A1+ A2+ A2+ C TDI TMS DATA DATA DATA DATA SPD LDTD TRST TDO V V V NC NC GND GND NC V GND CC CC CC CC [6] [4] [2] [0] SELB EN D TCLK RESET INSELA ULCA DATA DATA DATA SCAN TMEN3 V V NC GND GND GND GND NC V
ページ5に含まれる内容の要旨
CYV15G0104TRB [1] Pin Configuration (Bottom View) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A ROUT IN ROUT IN TOUT TOUT NC V NC V V GND GND GND NC V NC NC NC NC CC CC CC CC A2– A2– A1– A1– B2– B1– B ROUT IN ROUT IN TOUT TOUT NC NC NC NC V GND NC GND V V NC V NC V CC CC CC CC CC A2+ A2+ A1+ A1+ B2+ B1+ C TDO TRST LDTD SPD DATA DATA DATA DATA TMS TDI GND V NC GND GND NC NC V V V CC CC CC CC EN SELB [0] [2] [4] [6] D TMEN3 SCAN DATA DATA DATA ULCA INSELA RESET TCLK V NC V NC GND GND GND GN
ページ6に含まれる内容の要旨
CYV15G0104TRB Pin Definitions CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer Name I/O Characteristics Signal Description Transmit Path Data and Status Signals TXDB[9:0] LVTTL Input, Transmit Data Inputs. TXDB[9:0] data inputs are captured on the rising edge of the synchronous, transmit interface clock. The transmit interface clock is selected by the TXCKSELB latch sampled by via the device configuration interface. TXCLKB↑ or [2] REFCLKB↑ TXERRB LVTTL Output, Transmit Path Error
ページ7に含まれる内容の要旨
CYV15G0104TRB Pin Definitions (continued) CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer Name I/O Characteristics Signal Description BISTSTA LVTTL Output, BIST Status Output. When RXBISTA[1:0] = 10, BISTSTA (along with RXDA[1:0]) synchronous to the displays the status of the BIST reception. See Table 6 for the BIST status reported for RXCLKA ± output each combination of BISTSTA and RXDA[1:0]. When RXBISTA[1:0] ≠ 10, BISTSTA should be ignored. REPDOA Asynchronous to Reclocker Pow
ページ8に含まれる内容の要旨
CYV15G0104TRB Pin Definitions (continued) CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer Name I/O Characteristics Signal Description [4] SPDSELA 3-Level Select Serial Rate Select. The SPDSELA and SPDSELB inputs specify the operating signaling- SPDSELB static control input rate range of the receive and transmit PLL, respectively. LOW = 195 – 400 MBd MID = 400 – 800 MBd HIGH = 800 – 1500 MBd. INSELA LVTTL Input, Receive Input Selector. The INSELA input determines which external se
ページ9に含まれる内容の要旨
CYV15G0104TRB Pin Definitions (continued) CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer Name I/O Characteristics Signal Description [6] ROE2A Internal Latch Reclocker Differential Serial Output Driver 2 Enable. [6] ROE1A Internal Latch Reclocker Differential Serial Output Driver 1 Enable. [6] PABRSTB Internal Latch Transmit Clock Phase Alignment Buffer Reset. Factory Test Modes SCANEN2 LVTTL input, Factory Test 2. SCANEN2 input is for factory testing only. This input may be lef
ページ10に含まれる内容の要旨
CYV15G0104TRB Phase-Align Buffer Table 1. Operating Speed Settings Data from the Input Register is passed to the Phase-Align REFCLKB± Buffer, when the TXDB[9:0] input register is clocked using Frequency Signaling TXCLKBA (TXCKSELB = 0) or when REFCLKB is a half-rate SPDSELB TXRATEB (MHz) Rate (Mbps) clock (TXCKSELB = 1 and TXRATEB = 1). When the TXDB[9:0] input register is clocked using REFCLKB± LOW 1 reserved 195–400 (TXCKSELA = 1) and REFCLKB± is a full-rate clock 0 19.5–40 (TXRATEB = 0), t
ページ11に含まれる内容の要旨
CYV15G0104TRB INSELA input. The Serial Line Receiver inputs are differential, Range Controls and can accommodate wire interconnect and filtering losses The CDR circuit includes logic to monitor the frequency of the or transmission line attenuation greater than 16dB. For PLL Voltage Controlled Oscillator (VCO) used to sample the normal operation, these inputs should receive a signal of at incoming data stream. This logic ensures that the VCO least VI > 100 mV, or 200 mV peak-to-peak differential.
ページ12に含まれる内容の要旨
CYV15G0104TRB performed by an integrated PLL that tracks the frequency of When a driver is disabled via the configuration interface, it is the transitions in the incoming bit stream and aligns the phase internally powered down to reduce device power. If both of the internal bit-rate clock to the transitions in the selected reclocker serial drivers are in this disabled state, the internal serial data stream. reclocker logic is also powered down. The deserialization logic and parallel outputs will
ページ13に含まれる内容の要旨
CYV15G0104TRB the device configuration interface. When RXPLLPDA = 0, the initialization value of the latches upon the assertion of RESET. receive PLL and analog circuitry of the channel is disabled. Table 5 shows how the latches are mapped in the device. The transmit channel is controlled by the TOE1B and the Each row in the Table 5 maps to a 7-bit latch bank. There are TOE2B latches via the device configuration interface. The 6 such write-only latch banks. When WREN = 0, the logic value reclock
ページ14に含まれる内容の要旨
CYV15G0104TRB Table 4. Device Configuration and Control Latch Descriptions (continued) Name Signal Description RXPLLPDA Receive Channel Enable. The initialization value of the RXPLLPDA latch = 0. RXPLLPDA selects if the receive channel is enabled or powered-down. When RXPLLPDA = 0, the receive PLL and analog circuitry are powered-down. When RXPLLPDA = 1, the receive PLL and analog circuitry are enabled. RXBISTA[1:0] Receive Bist Disable / SMPTE Receive Enable. The initialization value of the
ページ15に含まれる内容の要旨
CYV15G0104TRB Table 5. Device Control Latch Configuration Table Reset ADDR Channel Type DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Value 0 A S 1 0 X X 0 0 RXRATEA 1011111 (000b) 1 A S SDASEL2A[1] SDASEL2A[0] SDASEL1A[1] SDASEL1A[0] X X TRGRATEA 1010110 (001b) 2 A D RXBISTA[1] RXPLLPDA RXBISTA[0] X ROE2A ROE1A X 1011001 (010b) 3 INTERNAL TEST REGISTERS (011b) DO NOT WRITE TO THESE ADDRESSES 4 (100b) 5 B S X X X X X 0 X 1011111 (101b) 6 B S X X X X 0 TXCKSELB TXRATEB 1010110 (110b) 7 B D X 0 X TX
ページ16に含まれる内容の要旨
CYV15G0104TRB Monitor Data Receive BIST Received Detected LOW {BISTSTA, RXDA[0], RX PLL RXDA[1 ]} = Out of Lock BIST_START (101) {BISTSTA, RXDA[0], RXDA[1]} = BIST_WAIT (111) Start of BIST Detected No Yes, {BISTSTA, RXDA[0], RXDA[1]} = BIST_DATA_COMPARE (000, 001) Compare Next Character Mismatch {BISTSTA, RXDA[0], RXDA[1]} = Match BIST_DATA_COMPARE (000, 001) Auto-Abort Yes Condition No End-of-BIST End-of-BIST No State State Yes, {BISTSTA, RXDA[0], RXDA[1]} = Yes, {BISTSTA, RXDA[0], RXD
ページ17に含まれる内容の要旨
CYV15G0104TRB Static Discharge Voltage.......................................... > 2000 V Maximum Ratings (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. User guidelines Latch-up Current..................................................... > 200 mA only, not tested.) Power-up Requirements Storage Temperature ..................................–65°C to +150°C The CYV15G0104TRB requires one power supply. The Ambient Temperature with Voltage on any input or I/O pin canno
ページ18に含まれる内容の要旨
CYV15G0104TRB CYV15G0104TRB DC Electrical Characteristics (continued) Parameter Description Test Conditions Min. Max. Unit V Output LOW Voltage 100Ω differential load V – 1.4 V – 0.7 V OLC CC CC (V Referenced) CC 150Ω differential load V – 1.4 V – 0.7 V CC CC V Output Differential Voltage 100Ω differential load 450 900 mV ODIF |(OUT+) − (OUT−)| 150Ω differential load 560 1000 mV Differential Serial Line Receiver Inputs: INA1±, INA2± [9] V Input Differential Voltage |(IN+) − (IN−)| 100 1200 mV D
ページ19に含まれる内容の要旨
CYV15G0104TRB CYV15G0104TRB AC Electrical Characteristics (continued) Parameter Description Min. Max Unit [16, 17, 18, 19] t TXCLKB Rise Time 0.2 1.7 ns TXCLKR [16, 17, 18, 19] t TXCLKB Fall Time 0.2 1.7 ns TXCLKF t Transmit Data Set-up Time to TXCLKB↑ (TXCKSELB = 0) 2.2 ns TXDS t Transmit Data Hold Time from TXCLKB↑ (TXCKSELB = 0) 1.0 ns TXDH f TXCLKOB Clock Frequency = 1x or 2x REFCLKB Frequency 19.5 150 MHz TOS t TXCLKOB Period=1/f 6.66 51.28 ns TXCLKO TOS t TXCLKOB Duty Cycle centered at
ページ20に含まれる内容の要旨
CYV15G0104TRB CYV15G0104TRB AC Electrical Characteristics (continued) Parameter Description Min. Max Unit t TRGCLKA HIGH Time (TRGRATEA = 1)(Half Rate) 5.9 ns TRGH [16] TRGCLKA HIGH Time (TRGRATEA = 0)(Full Rate) 2.9 ns t TRGCLKA LOW Time (TRGRATEA = 1)(Half Rate) 5.9 ns TRGL [16] TRGCLKA LOW Time (TRGRATEA = 0)(Full Rate) 2.9 ns [23] t TRGCLKA Duty Cycle 30 70 % TRGD [16, 17, 18] t TRGCLKA Rise Time (20%–80%) 2 ns TRGR [16, 17, 18] t TRGCLKA Fall Time (20%–80%) 2 ns TRGF [24] t TRGCLKA Freque
