ページ1に含まれる内容の要旨
CY7B991
CY7B992
Programmable Skew Clock Buffer
Features Functional Description
■ All output pair skew <100 ps typical (250 maximum) The CY7B991 and CY7B992 Programmable Skew Clock Buffers
(PSCB) offer user selectable control over system clock functions.
■ 3.75 to 80 MHz output operation
These multiple output clock drivers provide the system integrator
with functions necessary to optimize the timing of high perfor-
■ User selectable output functions
mance computer systems. Each of the eight indi
ページ2に含まれる内容の要旨
CY7B991 CY7B992 Pin Configuration PLCC/LCC 43 3 2 123130 5 29 2F0 3F1 4F0 6 28 GND 4F1 27 1F1 7 V 8 CCQ 26 1F0 CY7B991 V 9 25 V CCN CCN CY7B992 4Q1 24 10 1Q0 4Q0 23 11 1Q1 GND 12 22 GND GND 13 21 GND 14 15 16 17 18 19 20 Pin Definitions Signal Name IO Description REF I Reference frequency input. This input supplies the frequency and timing against which all functional variations are measured. FB I PLL feedback input (typically connected to one of the eight outputs). FS I Three level frequency r
ページ3に含まれる内容の要旨
CY7B991 CY7B992 Skew Select Matrix Block Diagram Description The skew select matrix contains four independent sections. Each Phase Frequency Detector and Filter section has two low skew, high fanout drivers (xQ0, xQ1), and two corresponding three level function select (xF0, xF1) inputs. The Phase Frequency Detector and Filter blocks accept inputs Table 2 shows the nine possible output functions for each section from the reference frequency (REF) input and the feedback (FB) as determined by the f
ページ4に含まれる内容の要旨
CY7B991 CY7B992 [4] Figure 1 shows the typical outputs with FB connected to a zero skew output. Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output FBInput REFInput 1Fx 3Fx 2Fx 4Fx (N/A) LM – 6t U LL LH – 4t U LM (N/A) – 3t U LH ML – 2t U ML (N/A) – 1t U MM MM 0t U MH (N/A) +1t U HL MH +2t U HM (N/A) +3t U HH HL +4t U (N/A) HM +6t U (N/A) LL/HH DIVIDED (N/A) HH INVERT Test Mode The TEST input is a three level input. In normal system If the TEST input is forced to its MID or HIGH st
ページ5に含まれる内容の要旨
CY7B991 CY7B992 Maximum Ratings Operating Range Operating outside these boundaries affects the performance and Ambient life of the device. These user guidelines are not tested. Range Temperature V CC Storage Temperature .................................–65 °C to +150 °C Commercial 0 °C to +70 °C 5V ± 10% Ambient Temperature with Industrial –40 °C to +85 °C 5V ± 10% Power Applied ............................................–55 °C to +125 °C [5] Military –55 °C to +125 °C 5V ± 10% Supply Voltage t
ページ6に含まれる内容の要旨
CY7B991 CY7B992 Electrical Characteristics [6] Over the Operating Range CY7B991 CY7B992 Parameter Description Test Conditions Min Max Min Max Unit V Output HIGH Voltage V = Min I = –16 mA 2.4 V OH CC OH V = Min, I =–40 mA V –0.75 CC OH CC V Output LOW Voltage V = Min, I = 46 mA 0.45 V OL CC OL V = Min, I = 46 mA 0.45 CC OL V Input HIGH Voltage 2.0 V V – V V IH CC CC CC (REF and FB inputs only) 1.35 V Input LOW Voltage –0.5 0.8 –0.5 1.35 V IL (REF and FB inputs only) V Three Level Input HIGH Min
ページ7に含まれる内容の要旨
CY7B991 CY7B992 Capacitance CMOS output buffer current and power dissipation specified at 50 MHz reference frequency. Parameter Description Test Conditions Max Unit C Input Capacitance T = 25 °C, f = 1 MHz, V = 5.0V 10 pF IN A CC AC Test Loads and Waveforms 5V 3.0V 2.0V R1=130 2.0V R1 V =1.5V V =1.5V R2=91 th th 0.8V 0.8V C =50pF(C =30 pF for –2 and –5 devices) L L C 0.0V (Includes fixture and probe capacitance) L R2 ≤1ns ≤1ns TTL AC Test Load (CY7B991) TTL Input Test Waveform (CY7B991) V CC V C
ページ8に含まれる内容の要旨
CY7B991 CY7B992 [2, 13] Switching Characteristics Over the Operating Range [14] [14] CY7B991–2 CY7B992–2 Parameter Description Min Typ Max Min Typ Max Unit [1, 2] f Operating Clock FS = LOW 15 30 15 30 MHz NOM Frequency in MHz [1, 2] FS = MID 25 50 25 50 [1, 2 , 3] [15] FS = HIGH 40 80 40 80 t REF Pulse Width HIGH 5.0 5.0 ns RPWH t REF Pulse Width LOW 5.0 5.0 ns RPWL t Programmable Skew Unit See Table 1 U t Zero Output Matched-Pair Skew 0.05 0.20 0.05 0.20 ns SKEWPR [16, 17] (XQ0, XQ1) [16, 18,1
ページ9に含まれる内容の要旨
CY7B991 CY7B992 Switching Characteristics [2, 13] Over the Operating Range (continued) CY7B991–5 CY7B992–5 Parameter Description Min Typ Max Min Typ Max Unit [1, 2] f Operating Clock FS = LOW 15 30 15 30 MHz NOM Frequency in MHz [1, 2] FS = MID 25 50 25 50 [1, 2 , 3] [15] FS = HIGH 40 80 40 80 t REF Pulse Width HIGH 5.0 5.0 ns RPWH t REF Pulse Width LOW 5.0 5.0 ns RPWL t Programmable Skew Unit See Table 1 U t Zero Output Matched-Pair Skew 0.1 0.25 0.1 0.25 ns SKEWPR [16, 17] (XQ0, XQ1) [16, 18
ページ10に含まれる内容の要旨
CY7B991 CY7B992 Switching Characteristics [2, 13] Over the Operating Range (continued) CY7B991–7 CY7B992–7 Parameter Description Min Typ Max Min Typ Max Unit [1, 2] f Operating Clock FS = LOW 15 30 15 30 MHz NOM Frequency in MHz [1, 2] FS = MID 25 50 25 50 [1, 2] [15] FS = HIGH 40 80 40 80 t REF Pulse Width HIGH 5.0 5.0 ns RPWH t REF Pulse Width LOW 5.0 5.0 ns RPWL t Programmable Skew Unit See Table 1 U t Zero Output Matched-Pair Skew 0.1 0.25 0.1 0.25 ns SKEWPR [16, 17] (XQ0, XQ1) [16, 18] t
ページ11に含まれる内容の要旨
CY7B991 CY7B992 AC Timing Diagrams t t REF RPWL t RPWH REF t t ODCV PD t ODCV FB t JR Q t t SKEWPR, SKEWPR, t t SKEW0,1 SKEW0,1 OTHERQ t SKEW2 t SKEW2 INVERTED Q t SKEW3,4 t SKEW3,4 t SKEW3,4 REF DIVIDED BY 2 t t SKEW1,3, 4 SKEW2,4 REF DIVIDED BY 4 Document Number: 38-07138 Rev. *B Page 11 of 19 [+] Feedback
ページ12に含まれる内容の要旨
CY7B991 CY7B992 Operational Mode Descriptions Figure 2. Zero Skew and Zero Delay Clock Driver REF LOAD Z 0 L1 FB SYSTEM REF CLOCK FS LOAD 4Q0 4F0 L2 4Q1 Z 0 4F1 3Q0 3F0 3Q1 LOAD 3F1 L3 2F0 2Q0 Z 0 2F1 2Q1 1F0 1Q0 1F1 L4 LOAD 1Q1 TEST Z 0 LENGTH L1 = L2 = L3 = L4 Figure 2 shows the PSCB configured as a zero skew clock buffer. In this mode the 7B991/992 is used as the basis for a low-skew clock distribution tree. When all of the function select inputs (xF0, xF1) are left open, the outputs are alig
ページ13に含まれる内容の要旨
CY7B991 CY7B992 F the FB and REF inputs and aligns their rising edges to ensure Figure 5. Frequency Multiplier with Skew Connectrions that all outputs have precise phase alignment. Clock skews are advanced by ±6 time units (tU) when using an REF output selected for zero skew as the feedback. A wider range of delays is possible if the output connected to FB is also skewed. Since “Zero Skew”, +tU, and –tU are defined relative to output FB 20 MHz groups, and since the PLL aligns the rising edges o
ページ14に含まれる内容の要旨
CY7B991 CY7B992 range since the highest frequency output is running at 20 MHz. of the divider adds to the skew between the different clock Figure 7 shows some of the functions that are selectable on the signals. 3Qx and 4Qx outputs. These include inverted outputs and These divided outputs, coupled with the Phase Locked Loop, outputs that offer divide-by-2 and divide-by-4 timing. An inverted enables the PSCB to multiply the clock rate at the REF input by output enables the system designer to clo
ページ15に含まれる内容の要旨
CY7B991 CY7B992 Figure 8. Board-to-Board Clock Distribution LOAD REF Z 0 L1 FB LOAD SYSTEM REF CLOCK FS L2 Z 0 4Q0 4F0 4Q1 4F1 3Q0 3F0 3Q1 LOAD 3F1 L3 2F0 2Q0 Z 0 2F1 2Q1 1F0 1Q0 L4 1F1 1Q1 FB TEST REF FS LOAD 4Q0 4F0 Z 4Q1 0 4F1 3Q0 3F0 3Q1 3F1 2F0 2Q0 LOAD 2F1 2Q1 1F0 1Q0 1F1 1Q1 TEST Figure 8 shows the CY7B991 and 992 connected in series to construct a zero skew clock distribution tree between boards. Delays of the downstream clock buffers are programmed to compensate for the wire length (tha
ページ16に含まれる内容の要旨
CY7B991 CY7B992 Ordering Information Accuracy Operating Ordering Code Package Type (ps) Range 250 CY7B991–2JC 32-Pb Plastic Leaded Chip Carrier Commercial CY7B991–2JCT 32-Pb Plastic Leaded Chip Carrier - Tape and Reel Commercial 500 CY7B991–5JC 32-Pb Plastic Leaded Chip Carrier Commercial CY7B991–5JCT 32-Pb Plastic Leaded Chip Carrier - Tape and Reel Commercial CY7B991–5JI 32-Pb Plastic Leaded Chip Carrier Industrial CY7B991–5JIT 32-Pb Plastic Leaded Chip Carrier - Tape and Reel Industrial 750 C
ページ17に含まれる内容の要旨
CY7B991 CY7B992 Military Specifications Group A Subgroup Testing DC Characteristics Parameter Subgroups V 1, 2, 3 OH V 1, 2, 3 OL V 1, 2, 3 IH V 1, 2, 3 IL V 1, 2, 3 IHH V 1, 2, 3 IMM V 1, 2, 3 ILL I 1, 2, 3 IH I 1, 2, 3 IL I 1, 2, 3 IHH I 1, 2, 3 IMM I 1, 2, 3 ILL I 1, 2, 3 CCQ I 1, 2, 3 CCN Package Diagrams Figure 9. 32-Pin Plastic Leaded Chip Carrier 51-85002-*B Document Number: 38-07138 Rev. *B Page 17 of 19 [+] Feedback
ページ18に含まれる内容の要旨
CY7B991 CY7B992 Package Diagrams (continued) Figure 10. 32-Pin Rectangular Leadless Chip Carrier MIL-STD-1835 C-12 51-85002-*B Document Number: 38-07138 Rev. *B Page 18 of 19 [+] Feedback
ページ19に含まれる内容の要旨
CY7B991 CY7B992 Document History Document Title: CY7B991/CY7B992 Programmable Skew Clock Buffer Document Number: 38-07138 Orig. of REV. ECN NO. Issue Date Description of Change Change ** 110247 12/19/01 SZV Change from Specification number: 38-00513 to 38-07138 *A 1199925 See ECN KVM/AESA Add Pb-free part numbers. Update package names in Ordering Information table. Remove Pentium reference on page 1. *B 1286064 See ECN AESA Change status to final © Cypress Semiconductor Corporation, 2001-2007
