ページ1に含まれる内容の要旨
CY2291
Three-PLL General Purpose EPROM
Programmable Clock Generator
Features Benefits
■ Three integrated phase-locked loops ■ Generates up to three custom frequencies from external
sources
■ EPROM programmability
■ Easy customization and fast turnaround
■ Factory-programmable (CY2291) or field-programmable
(CY2291F) device options ■ Programming support available for all opportunities
■ Low-skew, low-jitter, high-accuracy outputs ■ Meets critical industry standard timing requirements
■ Power-ma
ページ2に含まれる内容の要旨
CY2291 Pinouts Figure 1. CY2291- 20-pin SOIC 32XOUT 1 20 32XIN 19 32K 2 V BATT 3 18 CLKC SHUTDOWN/OE 17 4 V S2/SUSPEND DD 16 5 GND V DD XTALIN 15 S1 6 14 XTALOUT 7 S0 13 XBUF CLKF 8 CLKD 9 12 CLKA CPUCLK 10 CLKB 11 Pin Definitions Name Pin Number Description 32XOUT 1 32.768-kHz crystal feedback. 32K 2 32.768-kHz output (always active if VBATT is present). CLKC 3 Configurable clock output C. VDD 4, 16 Voltage supply. GND 5 Ground. [1] Reference crystal input or external reference clock input. X
ページ3に含まれる内容の要旨
CY2291 combination. The only limitation is that if a PLL is shut off, all Operation outputs derived from it must also be shut off. Suspending a PLL shuts off all associated logic, while suspending an output simply The CY2291 is a third-generation family of clock generators. The [3] forces a three-state condition. CY2291 is upwardly compatible with the industry standard ICD2023 and ICD2028 and continues their tradition by providing The CPUCLK can slew (transition) smoothly between 8 MHz and a hig
ページ4に含まれる内容の要旨
CY2291 Maximum Ratings (Exceeding maximum ratings may shorten the useful life of the Max. Soldering Temperature (10 sec) ......................... 260 °C device. User guidelines are not tested.) Junction Temperature.................................................. 150 °C Supply Voltage...............................................–0.5V to + 7.0V Package Power Dissipation...................................... 750 mW DC Input Voltage ...........................................–0.5V to + 7.0V Sta
ページ5に含まれる内容の要旨
CY2291 Electrical Characteristics, Commercial 3.3V Parameter Description Conditions Min. Typ. Max. Unit V HIGH-Level Output Voltage I = 4.0 mA 2.4 V OH OH V LOW-Level Output Voltage I = 4.0 mA 0.4 V OL OL V 32.768-kHz HIGH-Level I = 0.5 mA V V OH–32 OH BATT Output Voltage 0.5 V 32.768-kHz LOW-Level I = 0.5 mA 0.4 V OL–32 OL Output Voltage [9] V Except crystal pins 2.0 V HIGH-Level Input Voltage IH [9] V Except crystal pins 0.8 V LOW-Level Input Voltage IL I Input HIGH Current V = V –0.5V <1 10 μ
ページ6に含まれる内容の要旨
CY2291 Electrical Characteristics, Industrial 3.3V (continued) Parameter Description Conditions Min. Typ. Max. Unit [9] V Except crystal pins 2.0 V HIGH-Level Input Voltage IH [9] V Except crystal pins 0.8 V LOW-Level Input Voltage IL I Input HIGH Current V = V –0.5V < 1 10 μA IH IN DD I Input LOW Current V = +0.5V < 1 10 μA IL IN I Output Leakage Current Three-state outputs 250 μA OZ [10] I V = V max., 3.3V operation 50 70 mA V Supply Current DD DD DD DD Industrial I V Power Supply Current Shut
ページ7に含まれる内容の要旨
CY2291 Switching Characteristics, Commercial 5.0V (continued) Parameter Name Description Min. Typ. Max. Unit t Lock Time for Lock Time from Power Up < 0.25 1 ms 10B UPLL and SPLL Slew Limits CPU PLL Slew Limits CY2291 8 100 MHz CY2291F 8 90 MHz Switching Characteristics, Commercial 3.3V Parameter Name Description Min. Typ. Max. Unit t Output Period Clock output range, 3.3V CY2291 12.5 13000 ns 1 operation (80 MHz) (76.923 kHz) CY2291F 15 13000 ns (66.6 MHz) (76.923 kHz) [12] Output Duty 40% 5
ページ8に含まれる内容の要旨
CY2291 Switching Characteristics, Industrial 5.0V Parameter Name Description Min. Typ. Max. Unit t Output Period Clock output range, CY2291I 11.1 13000 ns 1 5V operation (90 MHz) (76.923 kHz) CY2291FI 12.5 13000 ns (80 MHz) (76.923 kHz) [12] 40% 50% 60% Output Duty Duty cycle for outputs, defined as t ÷ t 2 1 [11] Cycle f > 66 MHZ OUT [12] 45% 50% 55% Duty cycle for outputs, defined as t ÷ t 2 1 f < 66 MHZ OUT [13] t 35 ns Rise Time Output clock rise time 3 [13] t 2.5 4 ns Fall Time Output clock
ページ9に含まれる内容の要旨
CY2291 Switching Characteristics, Industrial 3.3V (continued) Parameter Name Description Min. Typ. Max. Unit t Output Enable Time for output to leave three-state mode after 10 15 ns 6 Time SHUTDOWN/OE goes HIGH [3, t Skew < 0.25 0.5 ns Skew delay between any identical or related outputs 7 12, 15] t CPUCLK Slew Frequency transition rate 1.0 20.0 MHz/ms 8 [14] t Peak-to-peak period jitter (t Max. – t min.),% of < 0.5 1 % Clock Jitter 9A 9A 9A clock period (f < 4 MHz) OUT [14] t Peak-to-peak peri
ページ10に含まれる内容の要旨
CY2291 Switching Waveforms Figure 5. CPU Frequency Change SELECT OLD SELECT NEW SELECT STABLE F t &t F 8 10 new old CPU Test Circuit V DD CLK out 0.1 μF C OUTPUTS LOAD V DD 0.1 μF GND Ordering Information Ordering Code Package Type Operating Range Operating Voltage [16] 20-Pin SOIC Industrial 3.3V or 5.0V CY2291FI Pb-Free CY2291SXC–XXX 20-Pin SOIC Commercial 5.0V CY2291SXC–XXXT 20-Pin SOIC – Tape and Reel Commercial 5.0V CY2291SXL–XXX 20-Pin SOIC Commercial 3.3V CY2291SXL–XXXT 20-Pin SOIC
ページ11に含まれる内容の要旨
CY2291 Package Diagram Figure 6. 20-Pin (300 MIL) SOIC Package Outline 51-85024 *C Document #: 38-07189 Rev. *C Page 11 of 12 [+] Feedback
ページ12に含まれる内容の要旨
CY2291 Document History Page Document Title: CY2291 Three-PLL General Purpose EPROM Programmable Clock Generator Document Number: 38-07189 Orig. of Submission REV. ECN Description of Change Change Date ** 110321 SZV 10/28/01 Change from Spec number: 38-00410 to 38-07189 *A 121836 RBI 12/14/02 Power up requirements added to Operating Conditions Information *B 276756 RGL 10/18/04 Added Lead Free Devices *C 2565316 AESA/KVM 09/16/08 Updated template. Added Note “Not recommended for new designs.”
