ページ1に含まれる内容の要旨
NI 5422 Specifications
NI PXI-5422 16-Bit 200 MS/s Arbitrary Waveform Generator
Unless otherwise noted, the following conditions were used for each
specification:
• Analog Filter enabled.
Signals terminated with 50 Ω .
Direct Path set to 1 V , Low-Gain Amplifier Path set to 2 V ,
pk-pk pk-pk
and High-Gain Amplifier Path set to 12 V .
pk-pk
Sample rate set to 200 MS/s and the Sample Clock Source set to
Divide-by-N.
Typical values are representative of an average unit operating at room
t
ページ2に含まれる内容の要旨
Environment ............................................................................................32 Safety, Electromagnetic Compatibility, and CE Compliance .................33 Physical....................................................................................................35 Where to Go for Support .........................................................................36 CH 0 (Channel 0 Analog Output, Front Panel Connector) Table 1. Specification Value Comments Number of 1
ページ3に含まれる内容の要旨
Table 1. (Continued) Specification Value Comments Amplitude and Offset Amplitude Amplitude (V ) 1. Amplitude pk-pk Range values assume Path Load Minimum Value Maximum Value the full scale of the DAC is Direct 50 Ω 0.707 1.00 utilized. If an 1 kΩ 1.35 1.91 amplitude smaller than Open 1.41 2.00 the minimum value is Low- 50 Ω 0.00564 2.00 desired, then Gain waveforms less 1 kΩ 0.0107 3.81 Amplifier than full scale of the DAC can Open 0.0113 4.00 be used. High- 50 Ω 0.0338 12.0 2. NI
ページ4に含まれる内容の要旨
Table 1. (Continued) Specification Value Comments Maximum Output Voltage Maximum Path Load Maximum Output Voltage (V) The combination Output of Amplitude and Direct 50 Ω ±0.500 Voltage Offset is limited by the Maximum 1 kΩ ±0.953 Output Voltage. Open ±1.000 Low- 50 Ω ±1.000 Gain 1 kΩ ±1.905 Amplifier Open ±2.000 High- 50 Ω ±6.000 Gain 1 kΩ ±11.43 Amplifier Open ±12.00 Accuracy DC Accuracy For the Low-Gain or High-Gain Amplifier Path: All paths are calibrated for ±0.2% of Amplitude ± 0.
ページ5に含まれる内容の要旨
Table 1. (Continued) Specification Value Comments Output Characteristics (Continued) Output Enable Software-selectable. When the Output Path is disabled, the — CH 0 Output is terminated to ground with a 1 W resistor equal to the selected output impedance. Maximum The CH 0 output can be connected to a 50 Ω , ±12 V — Output (±8 V for the Direct Path) source without sustaining any Overload damage. No damage occurs if the CH 0 output is shorted to ground indefinitely. Waveform The CH 0 output s
ページ6に含まれる内容の要旨
1 +0.4 dB +0.4 dB +0.4 dB +0.4 dB 0 –0.3 dB –0.3 dB –1 –1.2 dB –2 –3 Guaranteed Specification –3.4 dB Typical –4 1 10 100 Frequency (MHz) Figure 1. Normalized Passband Flatness, Direct Path 1 +0.3 dB +0.7 dB +0.7 dB +0.7 dB 0 –0.5 dB –0.7 dB –0.7 dB –1 –2 –3 Guaranteed Specification –3.4 dB Typical –4 1 10 100 Frequency (MHz) Figure 2. Normalized Passband Flatness, Low-Gain Amplifier Path NI 5422 Specifications 6 ni.com Flatness (dB) Flatness (dB)
ページ7に含まれる内容の要旨
1 +0.2 dB +0.2 dB +0.2 dB 0 –0.6 dB –1 –1.1 dB –1.1 dB –2 –3 Guaranteed Specification Typical –4 1 10 100 Frequency (MHz) Figure 3. Normalized Passband Flatness, High-Gain Amplifier Path 2.0 1.6 1.2 0.8 0.4 0 –0.4 –0.8 –1.2 –1.6 –2.0 05 10 20 30 400 60 70 80 90 100 Time (ns) Figure 4. Pulse Response, Low-Gain Amplifier Path with a 50 Ω Load © National Instruments Corporation 7 NI 5422 Specifications Amplitude (V) Flatness (dB)
ページ8に含まれる内容の要旨
Table 1. (Continued) Specification Value Comments Suggested Maximum Frequencies for Common Functions Function Path Disable the Analog Filter for Low-Gain High-Gain square, ramp, Direct Amplifier Amplifier and triangle functions. Sine 80 MHz 80 MHz 43 MHz Square Not Recommended 50 MHz 25 MHz Ramp Not Recommended 10 MHz 10 MHz Triangle Not Recommended 10 MHz 10 MHz 14 Not Recommended 43 MHz 12 Ω 10 8 6 Recommended Operation 4 2 0 0 20406080 Frequency (MHz) Figure 5. Recommended Sine Wav
ページ9に含まれる内容の要旨
Table 1. (Continued) Specification Value Comments Spectral Characteristics Spurious-Free Path Amplitude Dynamic –1 dBFS. Range Measured from (SFDR) with Low-Gain High-Gain DC to 100 MHz. Harmonics Direct Amplifier Amplifier Also called harmonic 1 MHz –70 dBc –65 dBc –66 dBc distortion. SFDR with 5 MHz –70 dBc –65 dBc –58 dBc harmonics at low 10 MHz –70 dBc –65 dBc –52 dBc amplitudes is limited by a 20 MHz –63 dBc –64 dBc –49 dBc –148 dBm/Hz 30 MHz –57 dBc –60 dBc –43 dBc noise floor. A
ページ10に含まれる内容の要旨
Table 1. (Continued) Specification Value Comments Spectral Characteristics (Continued) Spurious-Free Path Amplitude Dynamic –1 dBFS. Range Measured from (SFDR) DC to 100 MHz. without Low-Gain High-Gain SFDR without Harmonics Direct Amplifier Amplifier harmonics at low amplitudes is 1 MHz –85 dBFS –80 dBFS –77 dBFS limited by a –148 dBm/Hz 5 MHz –85 dBFS –80 dBFS –77 dBFS noise floor. 10 MHz –80 dBFS –80 dBFS –77 dBFS All values are typical and 20 MHz –80 dBFS –80 dBFS –77 dBFS inclu
ページ11に含まれる内容の要旨
10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 0 102030405060708090 100 Frequency (MHz) Figure 6. 10 MHz Single-Tone Spectrum, Direct Path, 200 MS/s (Typical) Note The noise floor in Figure 6 is limited by the measurement device. Refer to the Average Noise Density specification. © National Instruments Corporation 11 NI 5422 Specifications dBm
ページ12に含まれる内容の要旨
10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 0 102030405060708090 100 Frequency (MHz) Figure 7. 10.00001 MHz Single-Tone Spectrum, Low-Gain Amplifier Path, 200 MS/s (Typical) Note The noise floor in Figure 7 is limited by the measurement device. Refer to the Average Noise Density specification. NI 5422 Specifications 12 ni.com dBm
ページ13に含まれる内容の要旨
–30 Guaranteed Specification Typical –40 –44 dBc –49 dBc –50 –60 –67 dBc –70 –80 –90 0.1 1 10 100 Frequency (MHz) Figure 8. Total Harmonic Distortion, Direct Path –30 Guaranteed Specification Typical –40 –45 dBc –45 dBc –50 –60 dBc –60 –70 –80 –90 0.1 1 10 100 Frequency (MHz) Figure 9. Total Harmonic Distortion, Low-Gain Amplifier Path © National Instruments Corporation 13 NI 5422 Specifications Total Harmonic Distortion (dBc) Total Harmonic Distortion (dBc)
ページ14に含まれる内容の要旨
–30 Guaranteed Specification Typical –40 –45 dBc –50 –60 –70 –80 –90 0.1 1 10 100 Frequency (MHz) Figure 10. Total Harmonic Distortion, High-Gain Amplifier Path –50 –55 High-Gain –60 –65 Low-Gain –70 –75 Direct Path –80 –85 1 10 100 Frequency (MHz) Figure 11. Intermodulation Distortion, 200 kHz Separation (Typical) NI 5422 Specifications 14 ni.com Intermodulation Distortion (dBc) Total Harmonic Distortion (dBc)
ページ15に含まれる内容の要旨
10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 0 102030405060708090 100 Frequency (MHz) Figure 12. Direct Path, Two-Tone Spectrum (Typical) Note The noise floor in Figure 12 is limited by the noise floor of the measurement device. Refer to the Noise Floor specification. Sample Clock Table 2. Specification Value Comments Sources 1. Internal, Divide-by-N (N ≥ 1) Refer to the Onboard Clock 2. Internal, DDS-based, High-Resolution section for more 3. External, CLK IN (SMB front panel connector) info
ページ16に含まれる内容の要旨
Table 2. (Continued) Specification Value Comments Sample Rate Range and Resolution Sample Clock — Source Sample Rate Range Sample Rate Resolution Divide-by-N 5 MS/s to 200 MS/s Settable to (200 MS/s)/N (1 ≤ N ≤ 40) High 5 MS/s to 100 MS/s 1.06 µHz Resolution >100 MS/s to 200 MS/s 4.24 µHz CLK IN 5 MS/s to 200 MS/s Resolution determined by external clock source. DDC CLK IN 5 MS/s to 200 MS/s External Sample Clock duty PXI Star 5 MS/s to 105 MS/s cycle tolerance 40% to 60%. Trigger PXI_Trig<0.
ページ17に含まれる内容の要旨
Table 2. (Continued) Specification Value Comments System Phase Noise and Jitter (10 MHz Carrier) Sample Clock System Phase Noise 1. High- Source Density Resolution System Output Jitter (dBc/Hz) Offset specifications (Integrated from vary with 100 Hz 1 kHz 10 kHz 100 Hz to 100 kHz) Sample Rate. Divide-by-N –110 –122 –138 1.5 ps rms 2. Values are typical. High- –109 –120 –120 4.0 ps rms 1 Resolution 3. PXI Star 100 MS/s trigger specification is High- –108 –120 –122 4.2 ps rms valid when
ページ18に含まれる内容の要旨
Onboard Clock (Internal VCXO) Table 3. Specification Value Comments Clock Source Internal sample clocks can either be locked to a Reference — Clock using a phase-locked loop or be derived from the onboard VCXO frequency reference. Frequency ±25 ppm — Accuracy Phase-Locked Loop (PLL) Reference Clock Table 4. Specification Value Comments Sources 1. PXI_CLK10 (backplane connector) The PLL Reference Clock 2. CLK IN (SMB front panel connector) provides the reference frequency for the phase-
ページ19に含まれる内容の要旨
CLK IN (Sample Clock and Reference Clock Input, Front Panel Connector) Table 5. Specification Value Comments Connector SMB (jack) — Direction Input — Destinations 1. Sample Clock — 2. PLL Reference Clock Frequency 5 MHz to 200 MHz (Sample Clock Destination) — Range 5 MHz to 20 MHz (PLL Reference Clock destination) Input Voltage Sine wave: 0.65 V to 2.8 V into 50 Ω — pk-pk pk-pk Range (0 dBm to +13 dBm) Square wave: 0.2 V to 2.8 V into 50 Ω pk-pk pk-pk Maximum ±10 V — Input Overload Input 50 Ω
ページ20に含まれる内容の要旨
PFI 0 and PFI 1 (Programmable Function Interface, Front Panel Connectors) Table 6. Specification Value Comments Connectors Two SMB (jack) — Direction Bi-directional — Frequency DC to 200 MHz — Range As an Input (Trigger) Destinations Start Trigger — Maximum –2 V to +7 V — Input Overload V 2.0 V — IH V 0.8 V — IL Input 1 kΩ — Impedance As an Output (Event) Sources 1. Sample Clock divided by integer K (1 ≤ K ≤ 4,194,304) — 2. Sample Clock Timebase (200 MHz) divided by integer M (4 ≤ M ≤ 4,194,3
