ページ1に含まれる内容の要旨
DOCUMENT NUMBER
9S12DT128BDGV1/D
MC9S12DT128B
Device User Guide
V01.07
Covers also
MC9S12DG128B, MC9S12DJ128B,
MC9S12DB128B
Original Release Date: 18 June 2001
Revised: 16 Aug 2002
Motorola, Inc
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or
design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its paten
ページ2に含まれる内容の要旨
DOCUMENT NUMBER 9S12DT128BDGV1/D Revision History Version Revision Effective Author Description of Changes Number Date Date 18 Jun 18 June V01.00 Initial version (parent doc v2.03 dug for dp256). 2001 2001 23 July 23 July V01.01 Updated version after review 2001 2001 Changed Partname, added pierce mode, updated electrical 23 Sep 23 Sep V01.02 characteristics 2001 2001 some minor corrections 12 Oct 12 Oct V01.03 Replaced Star12 by HCS12 2001 2001 Updated electrical spec after MC-Qualification
ページ3に含まれる内容の要旨
MC9S12DT128B Device User Guide — V01.07 Table of Contents Section 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.3 Modes of Operation . . . . . . . . . . . . . . . . .
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MC9S12DT128B Device User Guide — V01.07 2.3.21 PH6 / KWH6 — Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.3.22 PH5 / KWH5 — Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.3.23 PH4 / KWH4 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.3.24 PH3 / KWH3 / SS1 — Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MC9S12DT128B Device User Guide — V01.07 2.3.57 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 2.4.1 VDDX,VSSX — Power & Ground Pins for I/O Drivers . . . . . . . . . . . . . . . . . . . . . . . .62 2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator 62 2.4.3 VDD1, VDD2,
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MC9S12DT128B Device User Guide — V01.07 Section 7 Clock and Reset Generator (CRG) Block Description . . . . . . . . .75 7.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 7.1.1 XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Section 8 Enhanced Capture Timer (ECT) Block Description. . . . . . . . . . . .75 Section 9 Analog to Digital Converter
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MC9S12DT128B Device User Guide — V01.07 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . .
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MC9S12DT128B Device User Guide — V01.07 8
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MC9S12DT128B Device User Guide — V01.07 List of Figures Figure 0-1 Order Partnumber Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Figure 1-1 MC9S12DT128B Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Figure 1-2 MC9S12DT128B Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Figure 2-1 Pin assignments 112 LQFP for MC9S12DT128B,MC9S12DG128B, MC9S12DJ128B, MC9S12DB128B48 Fi
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MC9S12DT128B Device User Guide — V01.07 10
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MC9S12DT128B Device User Guide — V01.07 List of Tables Table 0-1 Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 0-2 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 1-1 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 $0000 - $000F MEBI map 1 of 3 (Core User Guide) ......................
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MC9S12DT128B Device User Guide — V01.07 $01C0 - $01FF Reserved ..................................................................................................39 $0200 - $023F Reserved ..................................................................................................39 $0240 - $027F PIM (Port Integration Module) ..................................................................40 $0280 - $02BF CAN4 (Motorola Scalable CAN - MSCAN) ..............................................42
ページ13に含まれる内容の要旨
MC9S12DT128B Device User Guide — V01.07 Preface The Device User Guide provides information about the MC9S12DT128B device made up of standard HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A complete set of device manuals also includes the HCS12 Core User Guide and all the individual Block User Guides of the implemented modules. In a effort to reduce redundancy all module specific information is located only in the respective Block User Guide. If a
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MC9S12DT128B Device User Guide — V01.07 The following figure provides an ordering number example for the MC9S12D128B devices. MC9S12 DJ128B C FU Temperature Options Package Option C = -40˚C to 85˚C V = -40˚C to 105˚C Temperature Option M = -40˚C to 125˚C Device Title Package Options Controller Family FU = 80QFP PV = 112LQFP Figure 0-1 Order Partnumber Example See Table 0-2 for names and versions of the referenced documents throughout the Device User Guide. Table 0-2 Document References User Gu
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MC9S12DT128B Device User Guide — V01.07 Section 1 Introduction 1.1 Overview The MC9S12DT128B microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), 128K bytes of Flash EEPROM, 8K bytes of RAM, 2K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), two serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit analog-to-digital converters (ADC),
ページ16に含まれる内容の要旨
MC9S12DT128B Device User Guide — V01.07 – Digital filtering – Programmable rising or falling edge trigger • Memory – 128K Flash EEPROM – 2K byte EEPROM – 8K byte RAM • Two 8-channel Analog-to-Digital Converters – 10-bit resolution – External conversion trigger capability • Three 1M bit per second, CAN 2.0 A, B software compatible modules – Five receive and three transmit buffers – Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8x8bit – Four separate interrupt channels for R
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MC9S12DT128B Device User Guide — V01.07 • SAE J1850 Class B Data Communications Network Interface – Compatible and ISO Compatible for Low-Speed (<125 Kbps) Serial Data Communications in Automotive Applications • Inter-IC Bus (IIC) – Compatible with I2C Bus standard – Multi-master operation – Software programmable for one of 256 different serial clock frequencies • 112-Pin LQFP and 80-Pin QFP package options – I/O lines with 5V input and drive capability – 5V A/D converter inputs – Operation at 5
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MC9S12DT128B Device User Guide — V01.07 1.4 Block Diagram Figure 1-1 shows a block diagram of the MC9S12DT128B device. 18
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MC9S12DT128B Device User Guide — V01.07 Figure 1-1 MC9S12DT128B Block Diagram VRH VRH VRH 128K Byte Flash EEPROM ATD0 ATD1 VRL VRL VRL VDDA VDDA VDDA VSSA VSSA VSSA 8K Byte RAM AN0 PAD00 AN0 PAD08 2K Byte EEPROM AN1 PAD01 AN1 PAD09 AN2 AN2 PAD02 PAD10 VDDR AN3 PAD03 AN3 PAD11 VSSR AN4 PAD04 AN4 PAD12 VREGEN AN5 PAD05 AN5 PAD13 Voltage Regulator PAD06 PAD14 VDD1,2 AN6 AN6 VSS1,2 AN7 PAD07 AN7 PAD15 PIX0 PK0 XADDR14 Single-wire Background BKGD PIX1 PK1 XADDR15 Debug Module CPU12 PPAGE PIX2 PK2 XA
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MC9S12DT128B Device User Guide — V01.07 1.5 Device Memory Map Table 1-1 and Figure 1-2 show the device memory map of the MC9S12DT128B after reset. Note that after reset the EEPROM ($0000 – $07FF) is hidden by the register space ($0000 - $03FF) and the RAM ($0000 - $1FFF). The bottom 1K Bytes of RAM ($0000 - $03FF) are hidden by the register space. Table 1-1 Device Memory Map Size Address Module (Bytes) $0000 – $0017 CORE (Ports A, B, E, Modes, Inits, Test) 24 $0018 – $0019 Reserved 2 $001A – $
