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PCI/PCI-X Family of Gigabit Ethernet
Controllers Software Developer’s
Manual
82540EP/EM, 82541xx, 82544GC/EI, 82545GM/EM, 82546GB/EB, and
82547xx
317453-005
Revision 3.8
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Legal Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
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Revision History Date Version Comments June 2008 3.8 Updated EEPROM Word 21h bit descriptions (section 5.6.18). June 2008 3.7 Updated Sections 13.4.30 and 13.4.31 (added text stating to use the Interrupt Throttling Register (ITR) instead of registers RDTR and RADV for applications requiring an interrupt moderation mechanism). Jan 2007 3.6 Added a note to sections 13.4.20 and 13.4.21 for the 82547Gi/EI. Sept 2007 3.5 Updated section 13.4.16. May 2007 3.4 Updated section 6.4.1. Changed acronym “
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Note: This page is intentionally left blank. iv Software Developer’s Manual
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Contents Contents 1 Introduction ..................................................................................................................1 1.1 Scope ....................................................................................................................1 1.2 Overview ...............................................................................................................1 1.3 Ethernet Controller Features.................................................................
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Contents 3.2.5 Receive Descriptor Write-Back ..........................................................26 3.2.6 Receive Descriptor Queue Structure..................................................26 3.2.7 Receive Interrupts ..............................................................................28 3.2.8 82544GC/EI Receive Interrupts .........................................................31 3.2.9 Receive Packet Checksum Offloading...............................................31 3.3 Packe
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Contents 5.5 EEUPDATE Utility ...............................................................................................97 5.5.1 Command Line Parameters ...............................................................97 5.6 EEPROM Address Map.......................................................................................98 5.6.1 Ethernet Address (Words 00h-02h)..................................................103 5.6.2 Software Compatibility Word (Word 03h) ...........................
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Contents 6 Power Management...............................................................................................129 6.1 Introduction to Power Management ..................................................................129 6.2 Assumptions......................................................................................................129 6.3 D3cold support ..................................................................................................130 6.3.1 Power States.......
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Contents 10.1.3 Blink Control .....................................................................................180 11 PHY Functionality and Features ......................................................................183 11.1 Auto-Negotiation................................................................................................183 11.1.1 Overview ..........................................................................................183 11.1.2 Next Page Exchanges................
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Contents 12 Dual Port Characteristics....................................................................................203 12.1 Introduction .......................................................................................................203 12.2 Features of Each MAC......................................................................................203 12.2.1 PCI/PCI-X interface..........................................................................203 12.2.2 MAC Configuration Regist
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Contents 13.4.25 Receive Descriptor Base Address Low ............................................302 13.4.26 Receive Descriptor Base Address High ...........................................302 13.4.27 Receive Descriptor Length ...............................................................303 13.4.28 Receive Descriptor Head .................................................................303 13.4.29 Receive Descriptor Tail ....................................................................304 1
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Contents 13.7.10 Collision Count .................................................................................341 13.7.11 Defer Count......................................................................................342 13.7.12 Transmit with No CRS......................................................................342 13.7.13 Sequence Error Count......................................................................343 13.7.14 Carrier Extension Error Count................................
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Contents 13.8.5 Receive Data FIFO Packet Count ....................................................366 13.8.6 Transmit Data FIFO Head Register..................................................366 13.8.7 Transmit Data FIFO Tail Register ....................................................367 13.8.8 Transmit Data FIFO Head Saved Register ......................................367 13.8.9 Transmit Data FIFO Tail Saved Register .........................................368 13.8.10 Transmit Data FIFO Pa
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Contents Note: This page intentionally left blank. xiv Software Developer’s Manual
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Introduction Introduction 1 1.1 Scope This document serves as a software developer’s manual for 82546GB/EB, 82545GM/EM, 82544GC/EI, 82541(PI/GI/EI), 82541ER, 82547GI/EI, and 82540EP/EM Gigabit Ethernet Controllers. Throughout this manual references are made to the PCI/PCI-X Family of Gigabit Ethernet Controllers or Ethernet controllers. Unless specifically noted, these references apply to all the Ethernet controllers listed above. 1.2 Overview The PCI/PCI-X Family of Gigabit Ethernet Contro
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Introduction For the 82544GC/EI, when connected to an appropriate SerDes, it can alternatively provide an Ethernet interface for 1000 Base-SX or LX applications (IEEE 802.3z). Note: The 82546EB/82545EM is SerDes PICMG 2.16 compliant. The 82546GB/82545GM is SerDes PICMG 3.1 compliant. 82546GB/EB Ethernet controllers also provide features in an integrated dual-port solution comprised of two distinct MAC/PHY instances. As a result, they appear as multi-function PCI devices containing two identi
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Introduction • IEEE 802.3x compliant flow control support — Enables control of the transmission of Pause packets through software or hardware triggering — Provides indications of receive FIFO status • State-of-the-art internal transceiver (PHY) with DSP architecture implementation — Digital adaptive equalization and crosstalk — Echo and crosstalk cancellation — Automatic MDI/MDI-X crossover at all speeds and compensation for cable length — Media Independent Interfaces (MII) IEEE 802.3e for supp
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Introduction 1.3.5 Additional Performance Features • Provides adaptive Inter Frame Spacing (IFS) capability, enabling collision reduction in half duplex networks (82544GC/EI) • Programmable host memory receive buffers (256 B to 16 KB) • Programmable cache line size from 16 B to 128 B for efficient usage of PCI bandwidth • Implements a total of 64 KB (40 KB for the 82547GI/EI) of configurable receive and transmit data FIFOs. Default allocation is 48 KB for the receive data FIFO and 16 KB for th
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Introduction 1.3.6 Manageability Features (Not Applicable to the 82544GC/EI or 82541ER) • Manageability support for ASF 1.0 and AoL 2.0 by way of SMBus 2.0 interface and either: — TCO mode SMBus-based management packet transmit / receive support — Internal ASF-compliant TCO controller 1.3.7 Additional Ethernet Controller Features 1 • Implements ACPI register set and power down functionality supporting D0 and D3 states 1 • Supports Wake on LAN (WoL) • Provides four wire serial EEPROM interface
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Introduction 1.4 Conventions This document uses notes that call attention to important comments: Note: Indicates details about the hardware’s operations that are not immediately obvious. Read these notes to get information about exceptions, unusual situations, and additional explanations of some PCI/PCI-X Family of Gigabit Ethernet Controller features. 1.4.1 Register and Bit References This document refers to Ethernet controller register names using all capital letters. To refer to a specific
