ページ1に含まれる内容の要旨
SERVICE MANUAL
CD RECEIVER
4 497 20093 3
KD-LX555R
S
KD-LX555R
STD M 7 8 9 12
SOURCE
Area Suffix
E ------ Continental Europe
TABLE OF CONTENTS
1 Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Disassembly method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Adjustment. . . . . . . . .
ページ2に含まれる内容の要旨
SECTION 4 Description of major ICs 4.1 BA6956AN (IC830, IC831) : Reversible motor driver • Block diagram TSD CONTROL LOGIC 1 2 3 4 5 6 7 8 9 • Pin function • Truth table Pin No. Symbol Function FIN RIN OUT1 OUT2 MODE 1 VREF Output high voltage level control terminal H L H L Forward rotation mode 2 OUT2 Output terminal for motor L H L H Reverse rotation mode 3 RNF GND of driver division H H L L Break Mode 4 OUT1 Output terminal for motor L L OPEN OPEN Stand-by mode 5 VM Power supply for driver di
ページ3に含まれる内容の要旨
4.2 BR24C01AFV-W-X (IC1502) : EEPROM •Pin layout Vcc WP SCL SDA A0 A1 A2 GND • Block diagram 1kbit EEPROM ARRAY A0 1 8 Vcc 8bit 7bit ADDRESS SLAVE/WORD DATA A1 2 7 WP 7bit DECODER ADDRESS REGISTER REGISTER START STOP A2 3 6 SCL CONTROL LOGIC ACK GND 4 HIGH VOLTAGE GEN. Vcc LEVEL DETECT 5 SDA • Pin function Pin name I/O Description Vcc - Power supply GND - Ground (0v) A0,A1,A2 IN Slave address set SCL IN Serial clock input SDA IN / OUT Slave and word addressserial data input serial data outpu
ページ4に含まれる内容の要旨
4.3 BR24C32F (IC703) : EEPROM • Pin Layout • Pin layout & Block diagram VCC WP SCL SDA PIN NAME I/O Function VCC - Power Supply GND - Ground (0V) A0-A2 I Slave Address Set BR24C32/F SCL I Serial Clock Input SDA I/O Slave and Word Address. Serial Data Input$ Serial Data Output *1 WP I Write Protect Input A0 A1 A2 GND • Pin function A0 1 8 Vcc 32 Kbit EEPROM ARRAY 8bit 12bit ADDRESS SLAVE WORD DATA A1 2 7 WP 12bit DECODER ADDRESS REGISTER REGISTER START STOP A2 3 6 SCL CONTROL LOGIC ACK GND 4 HIG
ページ5に含まれる内容の要旨
4.5 BU1923F (IC51) : RDS decoder •Pin layout QUAL 1 16 RCLK RDATA 2 15 N.C. Vref 3 14 XO MUX 4 13 XI VDD1 5 12 VDD2 VSS1 6 11 VSS2 VSS3 7 10 T1 CMP 8 9 T2 • Block diagram VSS3 CMP 7 8 100k 4 MUX 120k 100k - 8th Switched capacitor filter + comparator Vref 3 anti-aliasing filter 16 5 RCLK VDD1 Analog Power supply 1 6 VSS1 QUAL PLL Bi-phase Differential PLL 2 12 57kHz RDATA VDD2 decoder decoder 1187.5Hz Digital RDS/ARI Power supply VSS2 11 Measurement Reference circuit clock 13 10 9 14 X0 Xl T2 T1
ページ6に含まれる内容の要旨
4.6 HA13164A (IC961) : Regulator • Terminal layout 12 34 56 78 9101112131415 • Block diagram +B C1 C2 100u 0.1u ACC VCC ACC 8 3 BATT.DET OUT 9 ANT OUT Surge Protector 2 C3 0.1u EXT OUT COMPOUT 1 BIAS TSD 6 C4 0.1u VDD OUT ANT CTRL 4 7 C7 0.1u CTRL 11 SW5VOUT 5 CD OUT 12 C5 0.1u ILMOUT AUDIO OUT 10 14 C8 C6 0.1u 10u 15 TAB 13 R1 GND GND ILM AJ UNIT R: C:F note1) TAB (header of IC) connected to GND • Pin function Pin No. Symbol Function 1 EXTOUT Output voltage is VCC-1 V when M or
ページ7に含まれる内容の要旨
4.7 HD74HCT126T-X : (IC1500,IC1503) Buffer • Pin arrangement • Pin function Input Output CA Y 1C 1 14 Vcc LX Z 1A 2 13 4C HL L HH H 1Y 3 12 4A H : High level L : Low level 2C 4 11 4Y X : Irrelevant Z : Off (Hhigh-impedance)state of a 3-stage output 2A 5 10 3C 2Y 6 9 3A GND 7 8 3Y • Block diagram 1A 1Y 1C 2A 2Y 2C 3A 3Y 3C 4A 4Y 4C (No.49793)1-37
ページ8に含まれる内容の要旨
4.8 LA47505 (IC941) : Power amp. • Terminal layout 6 20 9 11 7 1 Protective 8 circuit 5 12 3 2 Stand by 4 Switch Ripple Mute 10 22 Filter circuit 17 15 19 25 protective 18 circuit 13 21 14 23 Muting & On Time Control 16 24 Circuit 1-38 (No.49793)
ページ9に含まれる内容の要旨
• Terminal layout • Pin function Pin No. Symbol Function 1 AC CONT1 Header of IC 2 GND1 Power GND 3 OUTFR- Outpur(-) for front Rch 4 STBY Stand by input 5 OUTFR+ Output (+) for front Rch 6 Vcc1/2 Power input 7 OUTRR- Output (-) for rear Rch 8 GND2 Power GND 9 OUTRR+ Output (+) for rear Rch 10 VREF Ripple filter 11 INRR Rear Rch input 12 INFR Front Rch input 13 SGND Signal GND 14 INFL Front Lch input 15 INRL Rear Lch input 16 ONTIME Power on time control 17 OUTRL+ Output (+) for rear Lch 18 GND3
ページ10に含まれる内容の要旨
Level shift Level shift Level shift Level shift 4.9 LA6579H-X (IC1681) : 4-Channel bridge driver • Pin layout & Block diagram [H] 1 VIN1-A 28 VIN1 VIN1_SW [L] [H]: OP-AMP_A [L]: OP-AMP_B 2 VIN1+A 27 VIN1-B - + 3 VCCP1 26 VIN1+B 33k Signal system 4 VO+ 25 S-GND 11k power supply - + 5 VO- 24 VIN1-SW All outputs ON/OFF H : ON 6 VO2+ 23 MUTE MUTE L : OFF 7 VO2- 22 VREFIN Power system Power system GND GND FR FR FR FR Signal system power supply VO3+ 8 21 VCCS 3.3VREG (External:PTP Tr) VO3- 9 20 3
ページ11に含まれる内容の要旨
• Pin function Pin No. Symbol Function 1 VIN1-A CH1 input AMP_inverted input 2 VIN1+A CH1 input AMP_non-inverted input 3 VCCP1 CH1 and CH2 power stage power supply 4 VO1+ Output pin(+)for channel 1 5 VO1- CH1 output pin (-) for channel 1 6 VO2+ Output pin(+)for channel 2 7 VO2- Output pin(-)for channel 2 8 VO3+ Output pin(+)for channel 3 9 VO3- Output pin(-)for channel 3 10 VO4+ Output pin(+)for channel 4 11 VO4- Output pin(-)for channel 4 12 VCCP2 CH3 and CH4 power stage powr supply 13 VIN4 Inp
ページ12に含まれる内容の要旨
4.10 M61508FP (IC400) : E.volume • Pin layout & Block diagram VDD OUT 2 19 18 VDD OUT 1 CLOCK 20 17 DATA I/F SOFT TIMER VDD GND 21 16 SELECT DETECTOR VDD GND 22 15 NonFadaer OUT 2 NonFadaer OUT 1 NON FADER NON FADER VOLUME VOLUME FRONT OUT 2 FRONT OUT 1 23 14 REAR OUT2 24 13 REAR OUT1 VOLUME 2 + - - + FADER IN 2 FADER IN 1 25 12 A B A B 26 11 TONE OUT 2 TONE OUT 1 LOUDNESS LOUDNESS + + 3BAND TONE 3BAND TONE CONTROL CONTROL (BASS/MID/ (BASS/MID/
ページ13に含まれる内容の要旨
• Pin function Pin No. Symbol Function 1 REF IC signal GND 2 DEFP IN 1 Ope amp positive input 3 DEFN IN 1 Ope amp negative input 4 INA 1 Input selector ch1 input terminal 5 INB 1 Input selector ch1 input terminal 6 INC 1 Input selector ch1 input terminal 7 IND 1 Input selector ch1 input terminal 8 DEFN OUT 1 Operation outoutterminal (-) 9 SEL OUT 1 Input selector output terminal 10 VOL IN 1 Volume 1 input terminal 11 TONE OUT 1 Tone output terminal 12 FADER IN 1 Volume 2 input terminal 13 REAR
ページ14に含まれる内容の要旨
4.11 LC75878W (IC601) : LCD driver • Pin layout 100 ~ 76 1 75 ~ ~ 25 51 26 ~ 50 • Block diagram GENERAL COMMON SEGMENT DRIVER & LATCH PORT DRIVER CLOCK CONTROL OSC GENERATOR REGISTER VLCD CONTRAST SHIFT REGISTER ADJUSTER VLCD0 VLCD1 CCB VLCD2 INTERFACE VLCD3 VLCD4 VDD VSS • Pin function No. Symbol I/O Function 1~73 SEG1~SEG73 O Segment driver output pin. 74 SEG74 O Segment driver output pin. 75 SEG75 O Segment driver output pin. 76~83 COM8~COM1 O Common driver output pin. 84~87 P1~P4 O G
ページ15に含まれる内容の要旨
4.12 NJM4565V-X (IC1572) : Dual ope amp • Terminal layout & Pin function 1 AOUTPUT 8 1 2 A-INPUT 3 A+INPUT A + 7 2 - 4 V 5 B+INPUT B 6 B-INPUT + 6 3 - 7 B OUTPUT 8 V 5 4 4.13 NJU7241F25 (IC1651) : Regulator • Pin Layout • Block Diagram Short protect GND 1 5 STB VIN 2 3 VOUT VIN 2 STB 5 VOUT 3 4 NC Vref GND 1 1 GND 4.14 NJU7241F33 (IC1504) : Voltage regulator PIN FUNCTION 1. GND 1 5 2. VIN 3. VOUT 4. NC 2 5. STB 3 4 (No.49793)1-45
ページ16に含まれる内容の要旨
4.15 TA2157FN-X (IC1601):RF amp • Terminal layout 24 ~ 13 1 ~ 12 • Block diagram PEAK 13 12 20k 20k 50k 15k 14 11 40k 20k 15 10 20k 15k 20k 16 9 50 A 20k 12k 2k 50k 17 8 12k 20k 1k BOTTOM 18 7 PEAK 14k 2k 19 6 1.75k 240k 15pF x0.5 20 K 5 x2 240k 20k 15pF x0.5 21 1 4 x2 94k 60k 3 22 22k 60k 180k 94k 40pF 23 2 22k 3k 3k 24 1 PIN SEL TEB RFGC TEB (APC SW) (TE BAL) (AGC Gian) (TE BAL) VCTRLPIN Normal mode VCC APC ON -50% +12dB (0dB) Norm
ページ17に含まれる内容の要旨
• Pin function Pin No. Symbol I/O Function 1 VCC - 3.3V power supply pin 2 FNI I Main-beam amp input pin 3 FPI I Main-beam amp input pin 4 TPI I Sub-beam amp input pin 5 TNI I Sub-beam amp input pin 6 MDI I Monitor photo diode amp input pin 7 LDO O Laser diode amp output pin 8 SEL I APC circuit ON/OFF control signal, laser diode (LDO) control signal input or bottom/peak detection frequency change pin. APC SEL LDO circuit GND OFF Connected VCC through 1k resistor Hiz ON Control signal output V
ページ18に含まれる内容の要旨
4.16 TC94A14FA (IC1621) : DSP & DAC • Terminal layout & block daiagram 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 Clock 50 31 generator PWM D/A 51 30 LPF 52 1-bit 29 Servo DAC A/D control 53 28 54 27 55 26 ROM Digital equalizer Address automatic circuit 56 RAM adjustment circuit 25 57 24 Data CLV servo slicer 58 16 k 23 RAM 59 22 Synchronous guarantee EFM 60 VCO 21 decoder Audio out Digital 61 20 circuit output Micro- 62 controller 19 Sub code PLL interface decoder TMAX 63 18 64 17
ページ19に含まれる内容の要旨
Pin Symbol I/O Descroption No 17 TMAX O TMAX detection result output pin. TMAX Detection Result TMAX Output Longer than fixed period "PVDD3" Within fixed period "HiZ" Shorter than fixed period "AVSS3" 18 LPFN I Inverted input pin for PLL LPF amp. 19 LPFO O Output pin for PLL LPF amp. 20 PVREF - PLL-only VREF pin. 21 VCOF O VCO filter pin. 22 AV - Analog GND pin. SS3 23 SLCO O DAC output pin for data slice level generation. 24 RFI I RF signal input pin. Zin selectable by command. 25 AV - Analog
ページ20に含まれる内容の要旨
4.17 TC94A20F-011 (IC1652) : DAC/SRAM built in type D-ROM decoder+ MP3 decoder • Pin layout 48 33 32 49 17 64 116 • Block diagram 32 31 30 29 28 26 25 23 22 21 20 19 18 17 27 24 33 16 DAC DAC DIT 34 15 Bus 35 14 Switch 36 13 37 12 38 11 39 10 40 9 8 41 42 7 43 6 44 5 45 4 46 3 47 2 General Timing VCO inputbport 48 1 generator 51 52 54 55 56 57 58 61 62 64 49 50 53 59 60 63 1-50 (No.49793) Interrupt General output DRAM I/F Timer Flag control port Address calc. 2sets CROM ERAM SRAM I/F X-RAM Y-RAM
