ページ1に含まれる内容の要旨
C8051F340/1/2/3/4/5/6/7
Full Speed USB Flash MCU Family
Analog Peripherals HIgh Speed 8051 µC Core
- 10-Bit ADC - Pipelined instruction architecture; executes 70% of
• Up to 200 ksps
Instructions in 1 or 2 system clocks
• Built-in analog multiplexer with single-ended and
- 48 MIPS and 25 MIPS versions available.
differential mode
• VREF from external pin, internal reference, or V
- Expanded interrupt handler
DD
• Built-in temperature sensor
Memory
• External conversion start input option
- 43
ページ2に含まれる内容の要旨
C8051F340/1/2/3/4/5/6/7 NOTES: 2 Rev. 0.5
ページ3に含まれる内容の要旨
C8051F340/1/2/3/4/5/6/7 Table Of Contents 1. System Overview.................................................................................................... 17 1.1. CIP-51™ Microcontroller Core.......................................................................... 21 1.1.1. Fully 8051 Compatible.............................................................................. 21 1.1.2. Improved Throughput............................................................................... 21 1.1.3.
ページ4に含まれる内容の要旨
C8051F340/1/2/3/4/5/6/7 9.3. Interrupt Handler............................................................................................... 87 9.3.1. MCU Interrupt Sources and Vectors ........................................................ 87 9.3.2. External Interrupts.................................................................................... 87 9.3.3. Interrupt Priorities..................................................................................... 88 9.3.4. Interrupt Latency
ページ5に含まれる内容の要旨
C8051F340/1/2/3/4/5/6/7 14.Oscillators............................................................................................................. 135 14.1.Programmable Internal High-Frequency (H-F) Oscillator............................... 136 14.1.1.Internal H-F Oscillator Suspend Mode................................................... 136 14.2.Programmable Internal Low-Frequency (L-F) Oscillator ................................ 137 14.2.1.Calibrating the Internal L-F Oscillator..............
ページ6に含まれる内容の要旨
C8051F340/1/2/3/4/5/6/7 17.3.SMBus Operation ........................................................................................... 194 17.3.1.Arbitration............................................................................................... 195 17.3.2.Clock Low Extension.............................................................................. 196 17.3.3.SCL Low Timeout................................................................................... 196 17.3.4.SCL High (SMBus
ページ7に含まれる内容の要旨
C8051F340/1/2/3/4/5/6/7 21.2.Timer 2 .......................................................................................................... 251 21.2.1.16-bit Timer with Auto-Reload................................................................ 251 21.2.2.8-bit Timers with Auto-Reload................................................................ 252 21.2.3.Timer 2 Capture Modes: USB Start-of-Frame or LFO Falling Edge ...... 253 21.3.Timer 3 .................................................
ページ8に含まれる内容の要旨
C8051F340/1/2/3/4/5/6/7 NOTES: 8 Rev. 0.5
ページ9に含まれる内容の要旨
C8051F340/1/2/3/4/5/6/7 List of Figures and Tables 1. System Overview Table 1.1. Product Selection Guide ........................................................................ 18 Figure 1.1. C8051F340/1/4/5 Block Diagram........................................................... 19 Figure 1.2. C8051F342/3/6/7 Block Diagram........................................................... 20 Figure 1.3. On-Chip Clock and Reset ...................................................................... 22 F
ページ10に含まれる内容の要旨
C8051F340/1/2/3/4/5/6/7 8. Voltage Regulator (REG0) Table 8.1. Voltage Regulator Electrical Specifications............................................ 69 Figure 8.1. REG0 Configuration: USB Bus-Powered............................................... 70 Figure 8.2. REG0 Configuration: USB Self-Powered............................................... 70 Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator Disabled .............. 71 Figure 8.4. REG0 Configuration: No USB Connection.............
ページ11に含まれる内容の要旨
C8051F340/1/2/3/4/5/6/7 Figure 16.2. USB0 Register Access Scheme......................................................... 166 Table 16.2. USB0 Controller Registers .................................................................. 169 Figure 16.3. USB FIFO Allocation .......................................................................... 171 Table 16.3. FIFO Configurations ............................................................................ 172 Table 16.4. USB Transceiver Electrical C
ページ12に含まれる内容の要旨
C8051F340/1/2/3/4/5/6/7 Figure 20.10. SPI Slave Timing (CKPHA = 0)........................................................ 240 Figure 20.11. SPI Slave Timing (CKPHA = 1)........................................................ 240 Table 20.1. SPI Slave Timing Parameters ............................................................. 241 21.Timers Figure 21.1. T0 Mode 0 Block Diagram.................................................................. 244 Figure 21.2. T0 Mode 2 Block Diagram...........
ページ13に含まれる内容の要旨
C8051F340/1/2/3/4/5/6/7 List of Registers SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select . . . . . . . . . . . . . . . . . . . 48 SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select . . . . . . . . . . . . . . . . . . 49 SFR Definition 5.3. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SFR Definition 5.4. ADC0H: ADC0 Data Word MSB . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SFR Definition 5.5. ADC0L: ADC0 Data Word LSB . . . . .
ページ14に含まれる内容の要旨
C8051F340/1/2/3/4/5/6/7 SFR Definition 14.3. OSCLCN: Internal L-F Oscillator Control . . . . . . . . . . . . . . . . . . 138 SFR Definition 14.4. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 141 SFR Definition 14.5. CLKMUL: Clock Multiplier Control . . . . . . . . . . . . . . . . . . . . . . . 142 SFR Definition 14.6. CLKSEL: Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 SFR Definition 15.1. XBR0: Port I/O Crossbar Register 0 .
ページ15に含まれる内容の要旨
C8051F340/1/2/3/4/5/6/7 USB Register Definition 16.20. EINCSRH: USB0 IN Endpoint Control High Byte . . . 187 USB Register Definition 16.21. EOUTCSRL: USB0 OUT Endpoint Control Low Byte 189 USB Register Definition 16.22. EOUTCSRH: USB0 OUT Endpoint Control High Byte 190 USB Register Definition 16.23. EOUTCNTL: USB0 OUT Endpoint Count Low . . . . . 190 USB Register Definition 16.24. EOUTCNTH: USB0 OUT Endpoint Count High . . . . 190 SFR Definition 17.1. SMB0CF: SMBus Clock/Configuration . . . .
ページ16に含まれる内容の要旨
C8051F340/1/2/3/4/5/6/7 C2 Register Definition 23.2. DEVICEID: C2 Device ID . . . . . . . . . . . . . . . . . . . . . . . . 279 C2 Register Definition 23.3. REVID: C2 Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . 280 C2 Register Definition 23.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 280 C2 Register Definition 23.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 280 16 Rev. 0.5
ページ17に含まれる内容の要旨
C8051F340/1/2/3/4/5/6/7 1. System Overview C8051F340/1/2/3/4/5/6/7 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection. • High-speed pipelined 8051-compatible microcontroller core (up to 48 MIPS) • In-system, full-speed, non-intrusive debug interface (on-chip) • Universal Serial Bus (USB) Function Controller with eight flexible endpoint pipes, integrated trans- ceiver, and 1 kB FIFO RAM
ページ18に含まれる内容の要旨
C8051F340/1/2/3/4/5/6/7 Table 1.1. Product Selection Guide C8051F340-GQ 48 64k 4352 2 4 40 2 TQFP48 C8051F341-GQ 48 32k 2304 2 4 40 2 TQFP48 C8051F342-GQ 48 64k 4352 1 4 25 - 2 LQFP32 C8051F343-GQ 48 32k 2304 1 4 25 - 2 LQFP32 C8051F344-GQ 25 64k 4352 2 4 40 2 TQFP48 C8051F345-GQ 25 32k 2304 2 4 40 2 TQFP48 C8051F346-GQ 25 64k 4352 - 1 4 25 - 2 LQFP32 C8051F347-GQ 25 32k 2304 - 1 4 25 - 2 LQFP32 18 Rev. 0.5 Orderin
ページ19に含まれる内容の要旨
C8051F340/1/2/3/4/5/6/7 C2D Port I/O Configuration Debug / Programming Hardware P0.0 C2CK/RST P0.1 Digital Peripherals P0.2 Port 0 P0.3 Reset UART0 P0.4 Drivers CIP-51 8051 P0.5 UART1 P0.6/XTAL1 Power-On Controller Core P0.7/XTAL2 Reset P1.0 Timers 0, 1, P1.1 2, 3 Priority 64/32k Byte ISP FLASH P1.2 Port 1 P1.3 Supply Crossbar Program Memory P1.4/CNVSTR Drivers Decoder Monitor P1.5/VREF PCA/WDT P1.6 VDD P1.7 256 Byte RAM Power P2.0 Net SMBus P2.1 P2.2 Voltage SPI Port 2 P2.3 VREG 4/2k Byt
ページ20に含まれる内容の要旨
C8051F340/1/2/3/4/5/6/7 C2D Port I/O Configuration Debug / Programming P0.0 Hardware C2CK/RST Digital Peripherals P0.1 P0.2/XTAL1 Port 0 P0.3/XTAL2 Reset UART0 P0.4 Drivers CIP-51 8051 P0.5 P0.6/CNVSTR Power-On Controller Core P0.7/VREF P1.0 Reset Timers 0, 1, P1.1 2, 3 Priority 64/32 kB ISP FLASH P1.2 Port 1 Crossbar P1.3 Supply Program Memory P1.4 Drivers Monitor Decoder P1.5 PCA/WDT P1.6 VDD P1.7 256 Byte RAM Power P2.0 Net SMBus P2.1 P2.2 Voltage SPI Port 2 P2.3 VREG 4/2 kB XRAM P2.4
