ページ1に含まれる内容の要旨
MAX12527
19-3543; Rev 0; 2/05
Dual, 65Msps, 12-Bit, IF/Baseband ADC
General Description Features
The MAX12527 is a dual 3.3V, 12-bit analog-to-digital
♦ Direct IF Sampling Up to 400MHz
converter (ADC) featuring fully differential wideband
♦ Excellent Dynamic Performance
track-and-hold (T/H) inputs, driving internal quantizers.
70.4dB/69.8dB SNR at f = 70MHz/175MHz
IN
The MAX12527 is optimized for low power, small size,
84.4dBc/80.2dBc SFDR at f = 70MHz/175MHz
and high dynamic performance in inte
ページ2に含まれる内容の要旨
Dual, 65Msps, 12-Bit, IF/Baseband ADC ABSOLUTE MAXIMUM RATINGS V to GND ................................................................-0.3V to +3.6V DD DIFFCLK/SECLK, G/T, PD, SHREF, DIV2, OV to GND............-0.3V to the lower of (V + 0.3V) and +3.6V DIV4 to GND .........-0.3V to the lower of (V + 0.3V) and +3.6V DD DD DD INAP, INAN to GND ...-0.3V to the lower of (V + 0.3V) and +3.6V DD D0A–D11A, D0B–D11B, DAV, INBP, INBN to GND ...-0.3V to the lower of (V + 0.3V) and +3.6V DORA, DORB to
ページ3に含まれる内容の要旨
MAX12527 Dual, 65Msps, 12-Bit, IF/Baseband ADC ELECTRICAL CHARACTERISTICS (continued) (V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 10pF at digital outputs, V = -0.5dBFS (differen- DD DD L IN tial), DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f = 65MHz, T = -40°C to DD CLK A +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS f = 3MHz at -0.5dBFS 68.1 70.7 IN f = 32.
ページ4に含まれる内容の要旨
Dual, 65Msps, 12-Bit, IF/Baseband ADC ELECTRICAL CHARACTERISTICS (continued) (V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 10pF at digital outputs, V = -0.5dBFS (differen- DD DD L IN tial), DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f = 65MHz, T = -40°C to DD CLK A +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Clock Overdrive Recovery Time ±10% beyond full-sca
ページ5に含まれる内容の要旨
MAX12527 Dual, 65Msps, 12-Bit, IF/Baseband ADC ELECTRICAL CHARACTERISTICS (continued) (V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 10pF at digital outputs, V = -0.5dBFS (differen- DD DD L IN tial), DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f = 65MHz, T = -40°C to DD CLK A +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS I REFAP REF_P Sink Current V = 2.418V 1.2
ページ6に含まれる内容の要旨
Dual, 65Msps, 12-Bit, IF/Baseband ADC ELECTRICAL CHARACTERISTICS (continued) (V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 10pF at digital outputs, V = -0.5dBFS (differen- DD DD L IN tial), DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f = 65MHz, T = -40°C to DD CLK A +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS D 0A–D 11A, DO RA, D 0B–D 11B and D ORB Tri - S
ページ7に含まれる内容の要旨
MAX12527 Dual, 65Msps, 12-Bit, IF/Baseband ADC ELECTRICAL CHARACTERISTICS (continued) (V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), C ≈ 10pF at digital outputs, V = -0.5dBFS (differen- DD DD L IN tial), DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f = 65MHz, T = -40°C to DD CLK A +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TIMING CHARACTERISTICS (Figure 5) Clock P
ページ8に含まれる内容の要旨
Dual, 65Msps, 12-Bit, IF/Baseband ADC Typical Operating Characteristics (continued) (V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), C ≈ 5pF at digital outputs, V = -0.5dBFS, DD DD L IN DIFFCLK/SECLK = OV , PD = GND, G/T = GND, f = 65MHz (50% duty cycle), T = +25°C, unless otherwise noted.) DD CLK A TWO-TONE IMD PLOT TWO-TONE IMD PLOT FFT PLOT (32,768-POINT DATA RECORD) (16,384-POINT DATA RECORD) (16,384-POINT DATA RECORD) 0 0 0 f = 65.00352MHz CLK f = 65.00352MHz f = 65
ページ9に含まれる内容の要旨
MAX12527 Dual, 65Msps, 12-Bit, IF/Baseband ADC Typical Operating Characteristics (continued) (V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), C ≈ 5pF at digital outputs, V = -0.5dBFS, DD DD L IN DIFFCLK/SECLK = OV , PD = GND, G/T = GND, f = 65MHz (50% duty cycle), T = +25°C, unless otherwise noted.) DD CLK A SNR, SINAD vs. ANALOG INPUT AMPLITUDE -THD, SFDR vs. ANALOG INPUT AMPLITUDE SNR, SINAD vs. CLOCK SPEED (f = 65.00352MHz, f = 175MHz) (f = 65.00352MHz, f = 175MHz) (f
ページ10に含まれる内容の要旨
Dual, 65Msps, 12-Bit, IF/Baseband ADC Typical Operating Characteristics (continued) (V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), C ≈ 5pF at digital outputs, V = -0.5dBFS, DD DD L IN DIFFCLK/SECLK = OV , PD = GND, G/T = GND, f = 65MHz (50% duty cycle), T = +25°C, unless otherwise noted.) DD CLK A -THD, SFDR vs. ANALOG SUPPLY VOLTAGE SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE -THD, SFDR vs. DIGITAL SUPPLY VOLTAGE (f = 65.00352MHz, f = 175MHz) (f = 65.00352MHz, f = 70MHz) (f
ページ11に含まれる内容の要旨
MAX12527 Dual, 65Msps, 12-Bit, IF/Baseband ADC Typical Operating Characteristics (continued) (V = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), C ≈ 5pF at digital outputs, V = -0.5dBFS, DD DD L IN DIFFCLK/SECLK = OV , PD = GND, G/T = GND, f = 65MHz (50% duty cycle), T = +25°C, unless otherwise noted.) DD CLK A SNR, SINAD vs. TEMPERATURE -THD, SFDR vs. TEMPERATURE (f = 175MHz, A = -0.5dBFS) IN IN (f = 175MHz, A = -0.5dBFS) IN IN 72 90 SNR 70 85 SFDR 68 80 SINAD 66 75 -THD 6
ページ12に含まれる内容の要旨
Dual, 65Msps, 12-Bit, IF/Baseband ADC Pin Description PIN NAME FUNCTION 1, 4, 5, 9, GND Converter Ground. Connect all ground pins and the exposed paddle (EP) together. 13, 14, 17 2 INAP Channel A Positive Analog Input 3 INAN Channel A Negative Analog Input 6 COMA Channel A Common-Mode Voltage I/O. Bypass COMA to GND with a 0.1µF capacitor. Channel A Positive Reference I/O. Channel A conversion range is ±2/3 x (V - V ). Bypass REFAP REFAN REFAP with a 0.1µF capacitor to GND. Connect a 10µF and a
ページ13に含まれる内容の要旨
MAX12527 Dual, 65Msps, 12-Bit, IF/Baseband ADC Pin Description (continued) PIN NAME FUNCTION 30 D0B Channel B CMOS Digital Output, Bit 0 (LSB) 31 D1B Channel B CMOS Digital Output, Bit 1 32 D2B Channel B CMOS Digital Output, Bit 2 33 D3B Channel B CMOS Digital Output, Bit 3 34 D4B Channel B CMOS Digital Output, Bit 4 35 D5B Channel B CMOS Digital Output, Bit 5 36 D6B Channel B CMOS Digital Output, Bit 6 37 D7B Channel B CMOS Digital Output, Bit 7 38 D8B Channel B CMOS Digital Output, Bit 8 39 D9
ページ14に含まれる内容の要旨
Dual, 65Msps, 12-Bit, IF/Baseband ADC Pin Description (continued) PIN NAME FUNCTION Shared Reference Digital Input. SHREF = V : Shared reference enabled. DD SHREF = GND: Shared reference disabled. 66 SHREF When sharing the reference, externally connect REFAP and REFBP together to ensure that V REFAP equals V . Similarly, when sharing the reference, externally connect REFAN to REFBN together to REFBP ensure that V = V . REFAN REFBN Internal Reference Voltage Output. The REFOUT output voltage is 2
ページ15に含まれる内容の要旨
MAX12527 Dual, 65Msps, 12-Bit, IF/Baseband ADC CLOCK 12-BIT D0A TO D11A INAP DIGITAL OUTPUT DATA PIPELINE ERROR FORMAT DRIVERS ADC DORA INAN CORRECTION REFAP CHANNEL A REFERENCE COMA MAX12527 SYSTEM REFAN G/T REFIN INTERNAL REFERENCE DAV REFOUT GENERATOR SHREF OV DD REFBP CHANNEL B COMB REFERENCE SYSTEM REFBN INBP 12-BIT D0B TO D11B DIGITAL DATA OUTPUT PIPELINE ERROR FORMAT DRIVERS INBN ADC DORB CORRECTION CLOCK V DD DIFFCLK/SECLK CLOCK POWER CLKP CLOCK DUTY-CYCLE CONTROL PD AND DIVIDER EQUALIZE
ページ16に含まれる内容の要旨
Dual, 65Msps, 12-Bit, IF/Baseband ADC Table 1. Reference Modes V DD BOND WIRE V REFERENCE MODE REFIN INDUCTANCE MAX12527 1.5nH Internal Reference Mode. IN_P REFIN is driven by REFOUT either through a 35% V REFOUT C *C PAR SAMPLE direct short or a resistive divider. 2pF 4.5pF to 100% V = V / 2 COM_ DD V REFOUT V = V / 2 + 3/8 x V REF_P DD REFIN V DD BOND WIRE V = V / 2 - 3/8 x V REF_N DD REFIN INDUCTANCE Buffered External Reference Mode. 1.5nH IN_N An external 0.7V to 2.3V reference voltage is C
ページ17に含まれる内容の要旨
MAX12527 Dual, 65Msps, 12-Bit, IF/Baseband ADC Bypass REFIN and REFOUT to GND with a 0.1µF capac- duty-cycle independent. Due to this DLL, the itor. The REFIN input impedance is very large (>50MΩ ). MAX12527 requires approximately 100 clock cycles to When driving REFIN through a resistive divider, use acquire and lock to new clock frequencies. resistances ≥10kΩ to avoid loading REFOUT. Clock Input and Clock Control Lines Buffered external reference mode is virtually identical to The MAX12527 acc
ページ18に含まれる内容の要旨
Dual, 65Msps, 12-Bit, IF/Baseband ADC Table 2. Clock-Divider Control Inputs V DD DIV4 DIV2 FUNCTION S 1H Clock Divider Disabled MAX12527 00 f = f SAMPLE CLK 10kΩ Divide-by-Two Clock Divider 01 f = f / 2 SAMPLE CLK CLKP Divide-by-Four Clock Divider 10 10kΩ f = f / 4 DUTY-CYCLE SAMPLE CLK S 2H EQUALIZER 11 Not Allowed S 1L 10k Ω cuitry can be latched with the rising edge of the con- CLKN version clock (CLKP - CLKN). 10kΩ Data-Valid Output DAV is a single-ended version of the input clock that is
ページ19に含まれる内容の要旨
MAX12527 Dual, 65Msps, 12-Bit, IF/Baseband ADC externally isolates it from heavy capacitive loads. Refer the falling edge of DAV and are valid on the rising edge to the MAX12527 EV Kit schematic for recommendations of DAV. of how to drive the DAV signal through an external buffer. The MAX12527 output data format is either Gray code or two’s complement depending on the logic input G/T. Data Out-of-Range Indicator With G/T high, the output data format is Gray code. The DORA and DORB digital output
ページ20に含まれる内容の要旨
Dual, 65Msps, 12-Bit, IF/Baseband ADC 1 LSB = 4/3 x (V - V ) / 4096 1 LSB = 4/3 x (V - V ) / 4096 REFP REFN REFP REFN 2/3 x (V - V ) 2/3 x (V - V ) 2/3 x (V - V ) 2/3 x (V - V ) REFP REFN REFP REFN REFP REFN REFP REFN 0x7FF 0x800 0x7FE 0x801 0x7FD 0x803 0x001 0xC01 0x000 0xC00 0xFFF 0xC00 0x803 0x002 0x802 0x003 0x801 0x001 0x800 0x000 -2047 -2045 -1 0 +1 +2045 +2047 -2047 -2045 -1 0 +1 +2045 +2047 DIFFERENTIAL INPUT VOLTAGE (LSB) DIFFERENTIAL INPUT VOLTAGE (LSB) Figure 6. Two’s-Complement Trans
