ページ1に含まれる内容の要旨
TMS320C6202
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS072B – AUGUST 1998 – REVISED AUGUST 1999
Highest Performance Fixed-Point Digital 32-Bit External Memory Interface (EMIF)
Signal Processor (DSP) TMS320C6202 – Glueless Interface to Synchronous
– 4-ns Instruction Cycle Time Memories: SDRAM or SBSRAM
– 250-MHz Clock Rate – Glueless Interface to Asynchronous
– Eight 32-Bit Instructions/Cycle Memories: SRAM and EPROM
– 2000 MIPS
Four-Channel Bootloading
VelociTI Advanced Very L
ページ2に含まれる内容の要旨
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 GJL 352-PIN BALL GRID ARRAY (BGA) PACKAGE (BOTTOM VIEW) AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 11 3 5 7 91 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 GLS 384-PIN BALL GRID ARRAY (BGA) PACKAGE (BOTTOM VIEW) AB AA Y W V U T R P N M L K J H G F E D C B A 1 3 5 7 9 11 13 15 17 19 21 2 4 6 8 10 12 14 16 18 20 22 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ADVANCE IN
ページ3に含まれる内容の要旨
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 description The TMS320C62x DSPs (including the TMS320C6202 device) are the fixed-point DSP family in the TMS320C6000 platform. The TMS320C6202 (’C6202) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. With performance of u
ページ4に含まれる内容の要旨
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 functional block diagram Timers Data Memory Interrupt Selector Peripheral McBSPs Bus Controller XB Control DMA Control EMIF Control Data Memory Controller DMA Expansion Bus (XB) Controller Interface PLL CPU EMIF Power Down Program Memory Controller Boot- Config. Program Memory/Cache 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ADVANCE INFORMATION
ページ5に含まれる内容の要旨
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 CPU description The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determin
ページ6に含まれる内容の要旨
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 CPU description (continued) Program Memory 32-Bit Address 256-Bit Data ’C62x CPU Program Fetch Control Instruction Dispatch Registers Instruction Decode Data Path A Data Path B Control External Memory Register File A Register File B Logic Interface Test .S1 .M2 .L1 .M1 .D1 .D2 .S2 .L2 Emulation Interrupts Additional Peri
ページ7に含まれる内容の要旨
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 CPU description (continued) src1 src2 .L1 dst 8 long dst 8 long src 32 ST1 8 long src long dst Register dst Data Path A File A .S1 src1 (A0–A15) src2 dst src1 .M1 src2 LD1 dst
ページ8に含まれる内容の要旨
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 signal groups description CLKIN CLKOUT2 RESET CLKOUT1 NMI CLKMODE0 EXT_INT7 † CLKMODE1 Clock/PLL EXT_INT6 † CLKMODE2 EXT_INT5 Reset and PLLV EXT_INT4 Interrupts PLLG IACK INUM3 PLLF INUM2 INUM1 INUM0 TMS TDO IEEE Standard DMAC3 TDI 1149.1 DMAC2 TCK DMA Status (JTAG) DMAC1 TRST Emulation DMAC0 EMU1 EMU0 Power-Down PD Status RSV4 RSV3 RSV2 Reserved RSV1 RSV0 Control/Status † For GLS devices only Figur
ページ9に含まれる内容の要旨
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 signal groups description (continued) ARE Asynchronous 32 AOE ED[31:0] Data Memory AWE Control ARDY CE3 CE2 Memory Map CE1 SDA10 Synchronous Space Select CE0 SDRAS/SSOE Memory SDCAS/SSADS Control 20 SDWE/SSWE EA[21:2] Word Address BE3 HOLD/ HOLD BE2 HOLDA HOLDA Byte Enables BE1 BE0 EMIF (External Memory Interface) TOUT1 TOUT0 Timer 1 Timer 0 TINP1 TINP0 Timers McBSP0 CLKX0 Transmit FSX0 DX0 CLKR0 FS
ページ10に含まれる内容の要旨
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 signal groups description (continued) 32 XCLKIN XD[31:0] Data Clocks XFCLK XBE3/XA5 Byte-Enable XBE2/XA4 XOE Control/ XBE1/XA3 XRE Address XBE0/XA2 XWE/XWAIT I/O Port XCE3 Control XRDY Control XCE2 XCE1 XCE0 XHOLD Arbitration XHOLDA XCS XAS Host XCNTL Interface XW/R Control Expansion Bus XBLAST XBOFF Figure 4. Peripheral Signals (Continued) 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 ADVANCE
ページ11に含まれる内容の要旨
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions PIN NO. SIGNAL † † DESCRIPTION DESCRIPTION TYPE TYPE NAME GJL GLS CLOCK/PLL CLKIN C12 B10 I Clock Input CLKOUT1 AD20 Y18 O Clock output at full device speed Clock output at half of device speed CLKOUT2 AC19 AB19 O • Used for synchronous memory interface CLKMODE0 B15 B12 I Cl Clock mode selects (Note: CLKMODE1 and CLKMODE2 selects are for GLS devices only) k d l t (N t CLKMODE1 d
ページ12に含まれる内容の要旨
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) PIN NO. SIGNAL † † DESCRIPTION DESCRIPTION TYPE TYPE NAME GJL GLS EXPANSION BUS XCLKIN A9 C8 I Expansion bus synchronous host interface clock input XFCLK B9 A8 O Expansion bus FIFO interface clock output XD31 D15 C13 XD30 B16 A13 XD29 A17 C14 XD28 B17 B14 XD27 D16 B15 XD26 A18 C15 XD25 B18 A15 XD24 D17 B16 XD23 C18 C16 XD22 A20 A17 XD21 D18 B17 XD20 C19 C17 Ex Expansi
ページ13に含まれる内容の要旨
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) PIN NO. SIGNAL † † DESCRIPTION DESCRIPTION TYPE TYPE NAME GJL GLS EXPANSION BUS (CONTINUED) XBE3/XA5 C7 C5 Expansion bus multiplexed byte-enable control/address signals XBE2/XA4 D8 A4 I/O/Z I/O/Z • • A Act ct as as b byte yte ena enable ble ffor or h host ost por portt opera operation tion XBE1/XA3 A6 B5 • • Act as address for I/O port operation Act as address for I/O
ページ14に含まれる内容の要旨
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) PIN NO. SIGNAL † † DESCRIPTION DESCRIPTION TYPE TYPE NAME GJL GLS EMIF – ADDRESS (CONTINUED) EA10 P23 M20 EA9 R25 M21 EA8 R24 N22 EA7 R23 N20 EA6 T25 N21 O/Z External address (word address) EA5 T24 P21 EA4 U25 P20 EA3 T23 R22 EA2 V26 R21 EMIF – DATA ED31 AD8 Y6 ED30 AC9 AA6 ED29 AF7 AB6 ED28 AD9 Y7 ED27 AC10 AA7 ED26 AE9 AB8 ED25 AF9 Y8 ED24 AC11 AA8 ED23 AE10 AA9 ED2
ページ15に含まれる内容の要旨
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) PIN NO. SIGNAL † † DESCRIPTION DESCRIPTION TYPE TYPE NAME GJL GLS EMIF – ASYNCHRONOUS MEMORY CONTROL ARE V24 T21 O/Z Asynchronous memory read enable AOE V25 R20 O/Z Asynchronous memory output enable AWE U23 T22 O/Z Asynchronous memory write enable ARDY W25 T20 I Asynchronous memory ready input EMIF – SYNCHRONOUS DRAM (SDRAM)/SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL SDA
ページ16に含まれる内容の要旨
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) PIN NO. SIGNAL † † DESCRIPTION DESCRIPTION TYPE TYPE NAME GJL GLS MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP2) CLKS2 R3 N1 I External clock source (as opposed to internal) CLKR2 T2 N2 I/O/Z Receive clock CLKX2 R4 N3 I/O/Z Transmit clock DR2 V1 R2 I Receive data DX2 T4 R1 O/Z Transmit data FSR2 U2 P3 I/O/Z Receive frame sync FSX2 T3 P2 I/O/Z Transmit frame sync RESERVE
ページ17に含まれる内容の要旨
TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) PIN NO. SIGNAL † † DESCRIPTION DESCRIPTION TYPE TYPE NAME GJL GLS SUPPLY VOLTAGE PINS (CONTINUED) T1 J19 T26 K4 U3 K19 U24 L1 W3 M22 W24 N4 Y4 N19 Y23 P4 AD6 P19 AD10 T4 AD13 T19 AD17 U1 AD21 U4 AE7 U19 DV AE8 U22 S 3.3-V supply voltage DD AE19 W4 AE20 W6 AF11 W7 AF16 W9 – W10 – W13 – W14 – W16 – W17 – W19 – AB5 – AB9 – AB14 – AB18 A1 E7 A2 E8 A3 E10 A24 E11 A25 E12 A
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TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) PIN NO. SIGNAL † † DESCRIPTION DESCRIPTION TYPE TYPE NAME GJL GLS SUPPLY VOLTAGE PINS (CONTINUED) C2 F14 C3 F15 C4 F16 C23 G5 C24 G6 C25 G17 C26 G18 D3 H5 D4 H6 D5 H17 D22 H18 D23 J6 D24 J17 E4 K5 E23 K18 AB4 L5 AB23 L6 AC3 L17 AC4 L18 AC5 M5 AC22 M6 CV CV S S 1 18 .8-V V s su upp pplly y v voltage oltage DD DD AC23 M17 AC24 M18 AD1 N5 AD2 N18 AD3 P6 AD4 P17 AD23 R5 A
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TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) PIN NO. SIGNAL † † DESCRIPTION DESCRIPTION TYPE TYPE NAME GJL GLS SUPPLY VOLTAGE PINS (CONTINUED) AF26 U16 – V7 – V8 – V10 CV – V11 S 1.8-V supply voltage DD – V12 – V13 – V15 – V16 GROUND PINS A4 A1 A8 A5 A13 A12 A14 A18 A15 A22 A19 B2 A23 B21 B4 C1 B12 C3 B13 C20 B14 C22 B23 D5 C5 D8 C11 D11 V V GND GND Gro Ground und p pins ins SS SS C16 D12 C22 D15 D1 D18 D2 E4 D6
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TMS320C6202 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS072B – AUGUST 1998 – REVISED AUGUST 1999 Signal Descriptions (Continued) PIN NO. SIGNAL † † DESCRIPTION DESCRIPTION TYPE TYPE NAME GJL GLS GROUND PINS (CONTINUED) K1 F13 K26 F17 M1 F18 M26 H4 N1 H19 N2 J1 N25 J5 N26 J18 P1 J22 P2 K6 P25 K17 P26 L4 R1 L19 R26 M4 U1 M19 U26 N6 W1 N17 W26 P1 V V GND GND Gro Ground und pins pins SS SS AA4 P5 AA23 P18 AB3 P22 AB24 R4 AC1 R19 AC2 U5 AC6 U6 AC21 U10 AC25 U13 AC26 U17 AD5 U18 AD22 V4 AE4 V5 AE13 V
