ページ1に含まれる内容の要旨
REJ09B0112-0101Z
M32R-FPU
32 Software Manual
RENESAS 32-BIT RISC SINGLE-CHIP MICROCOMPUTER
Before using this material, please visit our website to confirm that this is the most
current document available.
Rev. 1.01
Revision date: Oct 31, 2003 www.renesas.com
ページ2に含まれる内容の要旨
Keep safety first in your circuit designs! • Renesas Technology Corporation puts the maximum effort into making semiconductor prod- ucts better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with ap- propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- fl
ページ3に含まれる内容の要旨
REVISION HISTORY M32R-FPU Software Manual Rev. Date Description Page Summary 1.00 Jan 08, 2003 – First edition issued 1.01 Oct 31, 2003 APPENDICES-3 Hexadecimal Instruction Code Table corrected (BTST instruction) APPENDICES-8 Appendix Figure 3.1.1 corrected Incorrect) *The E1 stage of the FDIV instruction requires 13 cycles. Correct) *The E1 stage of the FDIV instruction requires 14 cycles. APPENDICES-10 Appendix Figure 3.2.1 corrected Incorrect) LD1 Correct) LDI APPENDICES-13 Append
ページ4に含まれる内容の要旨
Table of contents CHAPTER 1 CPU PROGRAMMING MODEL 1.1 CPU register .......................................................................................................... 1-2 1.2 General-purpose registers ...................................................................................... 1-2 1.3 Control registers ..................................................................................................... 1-3 1.3.1 Processor status word register: PSW (CR0) .....................
ページ5に含まれる内容の要旨
CHAPTER 3 INSTRUCTIONS 3.1 Conventions for instruction description ................................................................... 3-2 3.2 Instruction description ............................................................................................. 3-5 APPENDIX Appendix 1 Hexadecimal Instraction Code .................................................................. Appendix-2 Appendix 2 Instruction List.............................................................................
ページ6に含まれる内容の要旨
This page left blank intentionally. M32R-FPU Software Manual (Rev.1.01)
ページ7に含まれる内容の要旨
CHAPTER 1 CPU PROGRAMMIING MODEL 1.1 CPU Register 1.2 General-purpose Registers 1.3 Control Registers 1.4 Accumulator 1.5 Program Counter 1.6 Data Format 1.7 Addressing Mode
ページ8に含まれる内容の要旨
CPU PROGRAMMING MODEL 1 1.1 CPU Register 1.1 CPU Register The M32R family CPU, with a built-in FPU (herein referred to as M32R-FPU) has 16 general-purpose registers, 6 control registers, an accumulator and a program counter. The accumulator is of 56-bit configuration, and all other registers are a 32- bit configuration. 1.2 General-purpose Registers The 16 general-purpose registers (R0 – R15) are of 32-bit width and are used to retain data and base addresses, as well as for integer calculations,
ページ9に含まれる内容の要旨
CPU PROGRAMMING MODEL 1 1.3 Control Registers 1.3 Control Registers There are 6 control registers which are the Processor Status Word Register (PSW), the Condition Bit Register (CBR), the Interrupt Stack Pointer (SPI), the User Stack Pointer (SPU), the Backup PC (BPC) and the Floating-point Status Register (FPSR). The dedicated MVTC and MVFC instructions are used for writing and reading these control registers. In addition, the SM bit, IE bit and C bit of the PSW can also be set by the SETPSW in
ページ10に含まれる内容の要旨
CPU PROGRAMMING MODEL 1 1.3 Control Registers 1.3.1 Processor Status Word Register: PSW (CR0) b0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 b15 0000 00 0 0 0 0000000 b16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 b31 BSM BIE BC SM IE C ? ? 00000?00000000 BPSW field PSW field < At reset release: "B'0000 0000 0000 0000 ??00 000? 0000 0000 > b Bit Name Function R W 0-15 No function assigned. Fix to "0". 0 0 16 BSM Saves value of SM bit when EIT occurs R W Backup SM Bit 17 BIE Saves value of IE bit when EIT oc
ページ11に含まれる内容の要旨
CPU PROGRAMMING MODEL 1 1.3 Control Registers 1.3.2 Condition Bit Register: CBR (CR1) The Condition Bit Register (CBR) is derived from the PSW register by extracting its Condition (C) bit. The value written to the PSW register's C bit is reflected in this register. The register can only be read. (Writing to the register with the MVTC instruction is ignored.) At reset release, the value of CBR is "H'0000 0000". b0 b31 CBR 0 0 00 00 00 00 0 0 0 0 0 0 0 0 000 0 00 0 0 000 0 0 C 1.3.3 Interrupt Stac
ページ12に含まれる内容の要旨
CPU PROGRAMMING MODEL 1 1.3 Control Registers 1.3.5 Floating-point Status Register: FPSR (CR7) b0 1 23456789 10 11 12 13 14 b15 FS FX FU FZ FO FV 0000 0 0 0 0 0 0 000000 b16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 b31 EZ EO EV DN CE CX CU CZ CO CV RM EX EU 0 0 00000100000000 b Bit Name Function R W 0 FS Reflects the logical sum of FU, FZ, FO and FV. R – Floating-point Exception Summary Bit 1 FX Set to "1" when an inexact exception occurs R W Inexact Exception Fla
ページ13に含まれる内容の要旨
CPU PROGRAMMING MODEL 1 1.3 Control Registers 21 EV 0: Mask EIT processing to be executed when an R W Invalid Operation Exception invalid operation exception occurs Enable Bit 1: Execute EIT processing when an invalid operation exception occurs 22 No function assigned. Fix to "0". 0 0 23 DN 0: Handle the denormalized number as a R W Denormalized Number Zero denormalized number Flash Bit (Note 2) 1: Handle the denormalized number as zero 24 CE 0: No unimplemented operation exception occ
ページ14に含まれる内容の要旨
CPU PROGRAMMING MODEL 1 1.3 Control Registers 1.3.6 Floating-point Exceptions (FPE) Floating-point Exception (FPE) occurs when Unimplemented Exception (UIPL) or one of the five exceptions specified in the IEEE754 standard (OVF/UDF/IXCT/ DIV0/IVLD) is detected. Each exception processing is outlined below. (1) Overflow Exception (OVF) The exception occurs when the absolute value of the operation result exceeds the largest describable precision in the floating-point format. The following table show
ページ15に含まれる内容の要旨
CPU PROGRAMMING MODEL 1 1.3 Control Registers (3) Inexact Exception (IXCT) The exception occurs when the operation result differs from a result led out with an infinite range of precision. The following table shows the operation results and the respective conditions in which each IXCT occurs. Operation Result (Content of the Destination Register) Occurrence Condition When the IXCT EIT processing is When the IXCT EIT processing is masked (Note 1) executed (Note 2) Overflow occurs in OVF Reference
ページ16に含まれる内容の要旨
CPU PROGRAMMING MODEL 1 1.3 Control Registers (5) Invalid Operation Exception (IVLD) The exception occurs when an invalid operation is executed. The following table shows the operation results and the respective conditions in which each IVLD occurs. Occurrence Condition Operation Result (Content of the Destination Register) When the IVLD EIT processing When the IVLD EIT is masked (Note 1) processing is executed (Note 2) Operation for SNaN operand +infinity -(+infinity), -infinity -(-infinity) QN
ページ17に含まれる内容の要旨
CPU PROGRAMMING MODEL 1 1.4 Accumulator 1.4 Accumulator The Accumulator (ACC) is a 56-bit register used for DSP function instructions. The accumulator is handled as a 64-bit register when accessed for read or write. When reading data from the accumulator, the value of bit 8 is sign-extended. When writing data to the accumulator, bits 0 to 7 are ignored. The accumulator is also used for the multiply instruction "MUL", in which case the accumulator value is destroyed by instruction execution. Use
ページ18に含まれる内容の要旨
CPU PROGRAMMING MODEL 1 1.6 Data Format 1.6 Data Format 1.6.1 Data Type The data types that can be handled by the M32R-FPU instruction set are signed or unsigned 8, 16, and 32-bit integers and single-precision floating-point numbers. The signed integers are represented by 2's complements. b0 b7 signed byte (8-bit) integer S b0 b7 unsigned byte (8-bit) integer b0 b15 signed halfword (16-bit) integer S b0 b15 unsigned halfword (16-bit) integer b0 b31 signed word (32-bit) integer S b0 b31 unsigned
ページ19に含まれる内容の要旨
CPU PROGRAMMING MODEL 1 1.6 Data Format 1.6.2 Data Format (1) Data format in a register The data sizes in the M32R-FPU registers are always words (32 bits). When loading byte (8-bit) or halfword (16-bit) data from memory into a register, the data is sign-extended (LDB, LDH instructions) or zero-extended (LDUB, LDUH instructions) to a word (32-bit) quantity before being loaded into the register. When storing data from a register into a memory, the 32-bit data, the 16-bit data on the LSB side and
ページ20に含まれる内容の要旨
CPU PROGRAMMING MODEL 1 1.6 Data Format (2) Data format in memory The data sizes in memory can be byte (8 bits), halfword (16 bits) or word (32 bits). Although byte data can be located at any address, halfword and word data must be located at the addresses aligned with a halfword boundary (least significant address bit = "0") or a word boundary (two low-order address bits = "00"), respectively. If an attempt is made to access memory data that overlaps the halfword or word boundary, an address e
