ページ1に含まれる内容の要旨
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DSP Microcomputers
ADSP-2181/ADSP-2183
FUNCTIONAL BLOCK DIAGRAM
FEATURES
PERFORMANCE POWERDOWN
PROGRAMMABLE
CONTROL I/O
30 ns Instruction Cycle Time @ 5.0 Volts
FLAGS
33 MIPS Sustained Performance MEMORY
DATA ADDRESS
GENERATORS PROGRAM
PROGRAM DATA
34.7 ns Instruction Cycle Time @ 3.3 Volts
SEQUENCER BYTE DMA
MEMORY MEMORY
DAG 1 DAG 0 CONTROLLER
Single-Cycle Instruction Execution
EXTERNAL
ADDRESS
Single-Cycle Context Switch
BUS
PROGRAM MEMORY ADDRESS
3-Bus Architecture Allows Dual Operand F
ページ2に含まれる内容の要旨
ADSP-2181/ADSP-2183 This takes place while the processor continues to: Additional Information This data sheet provides a general overview of ADSP-2181/ • receive and transmit data through the two serial ports ADSP-2183 functionality. For additional information on the • receive and/or transmit data through the internal DMA port architecture and instruction set of the processor, refer to the • receive and/or transmit data through the byte DMA port ADSP-2100 Family User’s Manual. For more informati
ページ3に含まれる内容の要旨
ADSP-2181/ADSP-2183 Program memory can store both instructions and data, permit- Each port can generate an internal programmable serial clock or ting the ADSP-2181/ADSP-2183 to fetch two operands in a accept an external serial clock. single cycle, one from program memory and one from data The ADSP-2181/ADSP-2183 provides up to 13 general-purpose memory. The ADSP-2181/ADSP-2183 can fetch an operand from flag pins. The data input and output pins on SPORT1 can be program memory and the next instruc
ページ4に含まれる内容の要旨
ADSP-2181/ADSP-2183 • SPORTs support serial data word lengths from 3 to 16 bits # and provide optional A-law and μ-law companding according Pin of Input/ to CCITT recommendation G.711. Name(s) Pins Output Function • SPORT receive and transmit sections can generate unique in- CLKOUT 1 O Processor Clock Output. terrupts on completing a data word transfer. SPORT0 5 I/O Serial Port I/O Pins • SPORTs can receive and transmit an entire circular buffer of SPORT1 5 I/O Serial Port 1 or Two External dat
ページ5に含まれる内容の要旨
ADSP-2181/ADSP-2183 Table I. Interrupt Priority & Interrupt Vector Addresses Power Down The ADSP-2181/ADSP-2183 processor has a low power Interrupt Vector feature that lets the processor enter a very low power dor- Source of Interrupt Address (Hex) mant state through hardware or software control. Here is a brief list of power-down features. Refer to the ADSP-2100 Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority) Family User’s Manual, Chapter 9 “System Interface” for de- Power Down (Nonma
ページ6に含まれる内容の要旨
ADSP-2181/ADSP-2183 When the IDLE (n) instruction is used, it effectively slows down The ADSP-2181/ADSP-2183 uses an input clock with a fre- the processor’s internal clock and thus its response time to in- quency equal to half the instruction rate; a 16.67 MHz input coming interrupts. The one-cycle response time of the standard clock yields a 30 ns processor cycle (which is equivalent to idle state is increased by n, the clock divisor. When an enabled 33 MHz). Normally, instructions are executed
ページ7に含まれる内容の要旨
ADSP-2181/ADSP-2183 Table II. Memory Architecture The ADSP-2181/ADSP-2183 provides a variety of memory and PMOVLAY Memory A13 A12:0 peripheral interface options. The key functional groups are Pro- gram Memory, Data Memory, Byte Memory, and I/O. 0 Internal Not Applicable Not Applicable Program Memory is a 24-bit-wide space for storing both in- 1 External 0 13 LSBs of Address struction opcodes and data. The ADSP-2181/ADSP-2183 has Overlay 1 Between 0x2000 16K words of Program Memory RAM on chip, a
ページ8に含まれる内容の要旨
ADSP-2181/ADSP-2183 There are 16,352 words of memory accessible internally when The CMS pin functions like the other memory select signals the DMOVLAY register is set to 0. When DMOVLAY is set to with the same timing and bus request logic. A 1 in the enable bit something other than 0, external accesses occur at addresses causes the assertion of the CMS signal at the same time as the 0x0000 through 0x1FFF. The external address is generated as selected memory select signal. All enable bits default
ページ9に含まれる内容の要旨
ADSP-2181/ADSP-2183 When the BWCOUNT register is written with a nonzero value Table VI. Boot Summary Table the BDMA circuit starts executing byte memory accesses with MMAP BMODE Booting Method wait states set by BMWAIT. These accesses continue until the count reaches zero. When enough accesses have occurred to 0 0 BDMA feature is used in default mode create a destination word, it is transferred to or from on-chip to load the first 32 program memory memory. The transfer takes one DSP cycle. DSP a
ページ10に含まれる内容の要旨
ADSP-2181/ADSP-2183 If the ADSP-2181/ADSP-2183 is performing an external INSTRUCTION SET DESCRIPTION memory access when the external device asserts the BR signal, The ADSP-2181/ADSP-2183 assembly language instruction set then it will not three-state the memory interfaces or assert the has an algebraic syntax that was designed for ease of coding and BG signal until the processor cycle after the access completes. readability. The assembly language, which takes full advantage of The instruction doe
ページ11に含まれる内容の要旨
ADSP-2181/ADSP-2183 Target Memory Interface These ADSP-2181/ADSP-2183 pins must be connected only to For your target system to be compatible with the EZ-ICE emu- the EZ-ICE connector in the target system. These pins have no lator, it must comply with the memory interface guidelines function except during emulation, and do not require pull-up or listed below. pull-down resistors. The traces for these signals between the ADSP-2181/ADSP-2183 and the connector must be kept as PM, DM, BM, IOM, & CM s
ページ12に含まれる内容の要旨
ADSP-2181–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS K Grade B Grade Parameter Min Max Min Max Unit V Supply Voltage 4.5 5.5 4.5 5.5 V DD T Ambient Operating Temperature 0 +70 –40 +85 °C AMB ELECTRICAL CHARACTERISTICS K/B Grades Parameter Test Conditions Min Max Unit 1, 2 V Hi-Level Input Voltage @ V = max 2.0 V IH DD V Hi-Level CLKIN Voltage @ V = max 2.2 V IH DD 1, 3 V Lo-Level Input Voltage @ V = min 0.8 V IL DD 1, 4, 5 V Hi-Level Output Voltage @ V = min OH DD I
ページ13に含まれる内容の要旨
ADSP-2181/ADSP-2183 ADSP-2181 * ABSOLUTE MAXIMUM RATINGS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V DD Output Voltage Swing . . . . . . . . . . . . . . –0.3 V to V + 0.3 V DD Operating Temperature Range (Ambient) . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (5 sec) TQFP . . . . . . . . . . . . . . . . +280°C Lead Tempera
ページ14に含まれる内容の要旨
ADSP-2181/ADSP-2183 2 (C × V × f ) is calculated for each output: DD ADSP-2181 # of ENVIRONMENTAL CONDITIONS 2 Pins × C × V × f DD Ambient Temperature Rating: 2 Address, DMS 8 × 10 pF × 5 V × 33.3 MHz = 66.6 mW T = T – (PD × θ ) AMB CASE CA 2 Data Output, WR 9 × 10 pF × 5 V × 16.67 MHz = 37.5 mW T = Case Temperature in °C CASE 2 RD 1 × 10 pF × 5 V × 16.67 MHz = 4.2 mW PD = Power Dissipation in W 2 CLKOUT 1 × 10 pF × 5 V × 33.3 MHz = 8.3 mW θ = Thermal Resistance (Case-to-Ambient) CA 116.6 mW θ =
ページ15に含まれる内容の要旨
ADSP-2181/ADSP-2183 t , is dependent on the capacitive load, C , and the current DECAY L ADSP-2181 load, i , on the output pin. It can be approximated by the fol- L CAPACITIVE LOADING lowing equation: Figures 10 and 11 show the capacitive loading characteristics of C •0.5V L the ADSP-2181. t = DECAY i L 30 from which T = +85°C V = 4.5V DD t = t – t DIS MEASURED DECAY 25 is calculated. If multiple pins (such as the data bus) are dis- abled, the measurement value is that of the last pin
ページ16に含まれる内容の要旨
ADSP-2181/ADSP-2183 ADSP-2183–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS K Grade B Grade Parameter Min Max Min Max Unit V Supply Voltage 3.0 3.6 3.0 3.6 V DD T Ambient Operating Temperature 0 +70 –40 +85 °C AMB ELECTRICAL CHARACTERISTICS K/B Grades Parameter Test Conditions Min Max Unit 1, 2 V Hi-Level Input Voltage @ V = max 2.0 V IH DD V Hi-Level CLKIN Voltage @ V = max 2.2 V IH DD 1, 3 V Lo-Level Input Voltage @ V = min 0.4 V IL DD 1, 4, 5 V Hi-Level Output Volta
ページ17に含まれる内容の要旨
ADSP-2181/ADSP-2183 ADSP-2183 * ABSOLUTE MAXIMUM RATINGS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to V + 0.5 V DD Output Voltage Swing . . . . . . . . . . . . . . –0.5 V to V + 0.5 V DD Operating Temperature Range (Ambient) . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (5 sec) TQFP . . . . . . . . . . . . . . . . +280°C * Stresses abo
ページ18に含まれる内容の要旨
ADSP-2181/ADSP-2183 2 (C × V × f ) is calculated for each output: DD ADSP-2183 ENVIRONMENTAL CONDITIONS # of 2 Ambient Temperature Rating: Pins × C × V × f DD 2 T = T – (PD × θ ) Address, DMS 8 × 10 pF × 3.3 V × 33.3 MHz = 29.0 mW AMB CASE CA 2 Data Output, WR 9 × 10 pF × 3.3 V × 16.67 MHz = 16.3 mW T = Case Temperature in °C CASE 2 RD 1 × 10 pF × 3.3 V × 16.67 MHz = 1.8 mW PD = Power Dissipation in W 2 CLKOUT 1 × 10 pF × 3.3 V × 33.3 MHz = 3.6 mW θ = Thermal Resistance (Case-to-Ambient) CA 50.7
ページ19に含まれる内容の要旨
ADSP-2181/ADSP-2183 ADSP-2183 from which t = t – t DIS MEASURED DECAY CAPACITIVE LOADING Figures 17 and 18 show the capacitive loading characteristics of is calculated. If multiple pins (such as the data bus) are dis- the ADSP-2183. abled, the measurement value is that of the last pin to stop driving. 30 T = +85°C 3.0V V = 3.0V DD INPUT 1.5V 25 0.0V 20 2.0V OUTPUT 1.5V 0.3V 15 Figure 19. Voltage Reference Levels for AC Measure- 10 ments (Except Output Enable/Disable) 5 Output Enable Time Ou
ページ20に含まれる内容の要旨
ADSP-2181/ADSP-2183 ADSP-2181 Parameter Min Max Unit Clock Signals and Reset Timing Requirements: t CLKIN Period 60 150 ns CKI t CLKIN Width Low 20 ns CKIL t CLKIN Width High 20 ns CKIH Switching Characteristics: t CLKOUT Width Low 0.5t – 7 ns CKL CK t CLKOUT Width High 0.5t – 7 ns CKH CK t CLKIN High to CLKOUT High 0 20 ns CKOH Control Signals Timing Requirements: 1 t RESET Width Low 5t ns RSP CK ADSP-2183 28.8 MHz Parameter Min Max Unit Clock Signals and Reset Timing Requirements:
