ページ1に含まれる内容の要旨
TMS320C64x DSP
Video Port/VCXO Interpolated Control (VIC) Port
Reference Guide
Literature Number: SPRU629
April 2003
ページ2に含まれる内容の要旨
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the t
ページ3に含まれる内容の要旨
Preface Read This First About This Manual This document describes the video port and VCXO interpolated control (VIC) port in the digital signal processors (DSPs) of the TMS320C6000 DSP family. Notational Conventions This document uses the following conventions. Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. Related Documentation From Texas Instruments The following documents describe the C6000 devices and related suppor
ページ4に含まれる内容の要旨
Trademarks Related Documentation From Texas Instruments / Trademarks Code Composer Studio Application Programming Interface Reference Guide (literature number SPRU321) describes the Code Composer Studio application programming interface (API), which allows you to program custom plug-ins for Code Composer. TMS320C6x Peripheral Support Library Programmer’s Reference (literature number SPRU273) describes the contents of the TMS320C6000 peripheral support library of functions and macros. It lists
ページ5に含まれる内容の要旨
Contents Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Provides an overview of the video port peripheral in the digital signal processors (DSPs) of the TMS320C6000 DSP family. Included are an overview of the video port functions, FIFO configu- rations, and signal mapping. 1.1 Video Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ページ6に含まれる内容の要旨
Contents 2.6 Video Port Throughput and Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.6.1 Video Capture Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.6.2 Video Display Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.7 Video Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ページ7に含まれる内容の要旨
Contents 3.8 TSI Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 3.8.1 TSI Capture Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 3.8.2 TSI Data Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 3.8.3 TSI Capture Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ページ8に含まれる内容の要旨
Contents 4 Video Display Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Discusses the video display port. 4.1 Video Display Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.1 Image Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.2 Video Display Counters . . . . . .
ページ9に含まれる内容の要旨
Contents 4.12.6 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) . . . . . . . . 4-64 4.12.7 Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) . . . . . . . 4-65 4.12.8 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) . . . . . . . . 4-67 4.12.9 Video Display Field 1 Image Offset Register (VDIMGOFF1) . . . . . . . . . . . . . . 4-68 4.12.10 Video Display Field 1 Image Size Register (VDIMGSZ1) . . . . . . . . . . . . . . . . 4-70 4.12.11 Video Display
ページ10に含まれる内容の要旨
Contents 6 VCXO Interpolated Control Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Provides an overview of the VCXO interpolated control (VIC) port. 6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ページ11に含まれる内容の要旨
Figures Figures 1–1 Video Port Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1–2 BT.656 Video Capture FIFO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1–3 8/10-Bit Raw Video Capture and TSI Video Capture FIFO Configuration . . . . . . . . . . . . . . 1-7 1–4 Y/C Video Capture FIFO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ページ12に含まれる内容の要旨
Figures 3–21 20-Bit Raw Data FIFO Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36 3–22 Parallel TSI Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38 3–23 Program Clock Reference (PCR) Header Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 3–24 System Time Clock Counter Operation . . . . . . . . . . . . . . . . . . . . . . . . .
ページ13に含まれる内容の要旨
Figures 4–17 10-Bit Y/C FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 4–18 10-Bit Y/C Dense FIFO Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 4–19 Chrominance Resampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 4–20 2x Co-Sited Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ページ14に含まれる内容の要旨
Figures 4–61 Video Display Clipping Register (VDCLIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-85 4–62 Video Display Default Display Value Register (VDDEFVAL) . . . . . . . . . . . . . . . . . . . . . . . . 4-86 4–63 Video Display Default Display Value Register (VDDEFVAL)—Raw Data Mode . . . . . . . 4-87 4–64 Video Display Vertical Interrupt Register (VDVINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-88 4–65 Video Display Field Bit Reg
ページ15に含まれる内容の要旨
Tables Tables 1–1 Video Capture Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1–2 Video Display Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 1–3 VDIN Data Bus Usage for Capture Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1–4 VDOUT Data Bus Usage for Display Modes . . . . . . . . . . . . . . . . . . . . . . .
ページ16に含まれる内容の要旨
Tables 3–24 TSI Capture Control Register (TSICTL) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 3-73 3–25 TSI Clock Initialization LSB Register (TSICLKINITL) Field Descriptions . . . . . . . . . . . . . 3-74 3–26 TSI Clock Initialization MSB Register (TSICLKINITM) Field Descriptions . . . . . . . . . . . . 3-75 3–27 TSI System Time Clock LSB Register (TSISTCLKL) Field Descriptions . . . . . . . . . . . . . . 3-76 3–28 TSI System Time Clock MSB Register (TSISTCLKM) Field De
ページ17に含まれる内容の要旨
Tables 4–26 Video Display Counter Reload Register (VDRELOAD) Field Descriptions . . . . . . . . . . . . 4-83 4–27 Video Display Display Event Register (VDDISPEVT) Field Descriptions . . . . . . . . . . . . . 4-84 4–28 Video Display Clipping Register (VDCLIP) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . 4-85 4–29 Video Display Default Display Value Register (VDDEFVAL) Field Descriptions . . . . . . . 4-87 4–30 Video Display Vertical Interrupt Register (VDVINT) Field Descriptions
ページ18に含まれる内容の要旨
Chapter 1 Overview This chapter provides an overview of the video port peripheral in the digital signal processors (DSPs) of the TMS320C6000 DSP family. Included are an overview of the video port functions, FIFO configurations, and signal mapping. Topic Page 1.1 Video Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Video Port FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
ページ19に含まれる内容の要旨
Video Port 1.1 Video Port The video port peripheral can operate as a video capture port, video display port, or transport stream interface (TSI) capture port. It provides the following functions: Video capture mode: Capture rate up to 80 MHz. Two channels of 8/10-bit digital video input from a digital camera or analog camera (using a video decoder). Digital video input is in YCbCr 4:2:2 format with 8-bit or 10-bit resolution multiplexed in ITU-R BT.656 format. One channel of Y/C 16/20-bi
ページ20に含まれる内容の要旨
Video Port TSI capture mode: Transport stream interface (TSI) from a front-end device such as demodulator or forward error correction device in 8-bit parallel format at up to 30 Mbytes/sec. The port generates up to three events per channel and one interrupt to the DSP. A high-level block diagram of the video port is shown in Figure 1–1. The port consists of two channels: A and B. A 5120-byte capture/display buffer is split- table between the two channels. The entire port (both channels) is a
