ページ1に含まれる内容の要旨
USB3290
Small Footprint Hi-Speed
USB 2.0 Device PHY with
UTMI Interface
Datasheet
PRODUCT FEATURES
Available in a 40 ball lead-free RoHS compliant
Applications
(4 x 4 x 0.9mm) VFBGA package
The USB3290 is the ideal companion to any ASIC, SoC
Interface compliant with the UTMI specification
or FPGA solution designed with a UTMI Hi-Speed USB
(60MHz, 8-bit bidirectional interface)
device (peripheral) core.
Only one required power supply (+3.3V)
Supports 480Mbps Hi-Speed (HS) and 12Mbps Ful
ページ2に含まれる内容の要旨
Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface Datasheet ORDER NUMBER(S): USB3290-FH FOR 40 BALL, VFBGA LEAD-FREE ROHS COMPLIANT PACKAGE USB3290-FH-TR FOR 40 BALL, VFBGA LEAD-FREE ROHS COMPLIANT PACKAGE (TAPE AND REEL) Reel Size is 4000 pieces. 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustr
ページ3に含まれる内容の要旨
Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface Datasheet Table of Contents Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chapter 2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chapte
ページ4に含まれる内容の要旨
Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface Datasheet List of Figures Figure 2.1 USB3290 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3.1 USB3290 Pinout - Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6.1 Full-Speed Driver VOH/IOH Characteristics for High-speed Capable Transceiver . . . . . . . . 17 Figure 6.2 Full-Speed
ページ5に含まれる内容の要旨
Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface Datasheet List of Tables Table 4.1 System Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4.2 Data Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4.3 USB I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ページ6に含まれる内容の要旨
Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface Datasheet Chapter 1 General Description The USB3290 provides the Physical Layer (PHY) interface to a USB 2.0 Device Controller. The IC is available in a 40 ball lead-free RoHS compliant VFBGA package. The small footprint package makes the USB3290 ideal for portable consumer electronics applications. 1.1 Product Description The USB3290 is an industrial temperature USB 2.0 physical layer transceiver (PHY) integrated circuit. SMSC’s
ページ7に含まれる内容の要旨
XO XI VDD3.3 ] OPMODE[1:0 DATA[7:0] TXREADY RXVALID RXERROR Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface Datasheet Chapter 2 Functional Block Diagram PLL and System 1.8V PWR XTAL OSC Clocking Regulator Control TX TX LOGIC RPU_EN 1.5kΩ TX State VPO Machine VMO FS Parallel to OEB TX Serial Conversion RESET HS_DATA Bit Stuff SUSPENDN HS_DRIVE_ENABLE HS XCVRSELECT NRZI HS_CS_ENABLE TX Encode TERMSELECT DP R DM LINESTATE[1:0] X CLKOUT RX FS SE+ LOGIC VP RX State TXVALID VM Mac
ページ8に含まれる内容の要旨
Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface Datasheet Chapter 3 Pinout 17 2 3 4 5 6 RB REN XI XO V33 RXE RXV A XSEL GND V33 V18A VIO GND D0 B TXR TSEL V18 D1 C SPDN TXV D2 D3 D RST DM D4 D5 E DP GND RXA OM0 LS1 GND D6 F V33 V33 OM1 CLK LS0 VIO D7 G TOP VIEW Figure 3.1 USB3290 Pinout - Top View Revision 1.5 (11-02-07) 8 SMSC USB3290 DATASHEET
ページ9に含まれる内容の要旨
Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface Datasheet Chapter 4 Interface Signal Definition Table 4.1 System Interface Signals ACTIVE NAME DIRECTION LEVEL DESCRIPTION RESET Input High Reset. Reset all state machines. After coming out of reset, must wait 5 rising edges of clock before asserting (RST) TXValid for transmit. See Section 7.8.3 XCVRSELECT Input N/A Transceiver Select. This signal selects between the FS (XSEL) and HS transceivers: 0: HS transceiver enable
ページ10に含まれる内容の要旨
Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface Datasheet Table 4.2 Data Interface Signals ACTIVE NAME DIRECTION LEVEL DESCRIPTION DATA[7:0] Bidirectional High Data bus. 8-bit Bidirectional mode. (D7) . TXVALID DATA[7:0] . 0 output . (D0) 1 input TXVALID Input High Transmit Valid. Indicates that the DATA bus is valid for transmit. The (TXV) assertion of TXVALID initiates the transmission of SYNC on the USB bus. The negation of TXVALID initiates EOP on the USB. Control in
ページ11に含まれる内容の要旨
Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface Datasheet Table 4.5 Power and Ground Signals ACTIVE NAME DIRECTION LEVEL DESCRIPTION VDD3.3 N/A N/A 3.3V Supply. Provides power for USB 2.0 Transceiver, UTMI+ Digital, Digital I/O, and Regulators. (V33) (VIO) REG_EN Input High On-Chip 1.8V regulator enable. Connect to ground to disable both of the on chip (VDDA1.8 and VDD1.8) regulators. When (REN) regulators are disabled: External 1.8V must be supplied to VDDA1.8 and VDD1.8
ページ12に含まれる内容の要旨
Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface Datasheet Chapter 5 Limiting Values Table 5.1 Absolute Maximum Ratings PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Maximum DP and DM V -0.3 5.5 V MAX_5V voltage to Ground Maximum VDD1.8 and V -0.3 2.5 V MAX_1.8V VDDA1.8 voltage to Ground Maximum 3.3V Supply V -0.3 4.0 V MAX_3.3V Voltage to Ground Maximum I/O Voltage to V -0.3 4.0 V I Ground o Storage Temperature T -55 150 C STG ESD PERFORMANCE All Pins V Human Body Model ±5 kV H
ページ13に含まれる内容の要旨
Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface Datasheet Chapter 6 Electrical Characteristics Table 6.1 Electrical Characteristics: Supply Pins (Note 6.1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Unconfigured Current I Device Unconfigured 55 mA AVG(UCFG) FS Idle Current I FS idle not data transfer 55 mA AVG(FS) FS Transmit Current I FS current during data 60.5 mA AVG(FSTX) transmit FS Receive Current I FS current during data 57.5 mA AVG(FSRX) receive HS Idle Current I HS
ページ14に含まれる内容の要旨
Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface Datasheet Table 6.3 DC Electrical Characteristics: Analog I/O Pins (DP/DM) (Note 6.3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS FS FUNCTIONALITY Input levels Differential Receiver Input V | V(DP) - V(DM) | 0.2 V DIFS Sensitivity Differential Receiver V 0.8 2.5 V CMFS Common-Mode Voltage Single-Ended Receiver Low V 0.8 V ILSE Level Input Voltage Single-Ended Receiver High V 2.0 V IHSE Level Input Voltage Single-Ended Receiver V
ページ15に含まれる内容の要旨
Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface Datasheet Table 6.3 DC Electrical Characteristics: Analog I/O Pins (DP/DM) (Note 6.3) (continued) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS High Speed High Level V 45Ω load 360 440 mV HSOH Output Voltage (DP/DM referenced to GND) 45Ω load -10 10 mV High Speed IDLE Level V OLHS Output Voltage (DP/DM referenced to GND) Chirp-J Output Voltage V HS termination resistor 700 1100 mV CHIRPJ (Differential) disabled, pull-up resistor
ページ16に含まれる内容の要旨
Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface Datasheet Table 6.5 Dynamic Characteristics: Digital UTMI Pins (Note 6.5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS UTMI Timing DATA[7:0] T Output Delay. Measured 25ns PD from PHY output to the RXVALID rising edge of CLKOUT RXACTIVE RXERROR LINESTATE[1:0] TXREADY DATA[7:0] T Setup Time. Measured 5ns SU from PHY input to the TXVALID rising edge of CLKOUT. OPMODE[1:0] XCVRSELECT TERMSELECT DATA[7:0] T Hold time. Measured from
ページ17に含まれる内容の要旨
Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface Datasheet Drive High Iout (mA) Slope = 1/49.5 Ohm -6.1 * |VOH| Test Limit Slope = 1/40.5 Ohm -10.71 * |VOH| 0 0.566*VOH 0.698*VOH VOH 0 Vout (Volts) Figure 6.1 Full-Speed Driver VOH/IOH Characteristics for High-speed Capable Transceiver Drive Low Iout Slope = 1/40.5 Ohm (mA) Test Limit 10.71 * |VOH| 22 Slope = 1/49.5 Ohm 0 1.09V 0.434*VOH VOH 0 Vout (Volts) Figure 6.2 Full-Speed Driver VOL/IOL Characteri
ページ18に含まれる内容の要旨
Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface Datasheet 6.2 High-speed Signaling Eye Patterns High-speed USB signals are characterized using eye patterns. For measuring the eye patterns 4 points have been defined (see Figure 6.3). The Universal Serial Bus Specification Rev.2.0 defines the eye patterns in several ‘templates’. The two templates that are relevant to the PHY are shown below. TP1 TP2 TP3 TP4 USB Cable Traces Traces Transceiver A B Transceiver Connector Conne
ページ19に含まれる内容の要旨
Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface Datasheet The eye pattern in Figure 6.4 defines the transmit waveform requirements for a hub (measured at TP2 of Figure 6.3) or a device without a captive cable (measured at TP3 of Figure 6.3). The corresponding signal levels and timings are given in table below. Time is specified as a percentage of the unit interval (UI), which represents the nominal bit duration for a 480 Mbit/s transmission rate. Level 1 400mV Differential
ページ20に含まれる内容の要旨
Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface Datasheet The eye pattern in Figure 6.5 defines the receiver sensitivity requirements for a hub (signal applied at test point TP2 of Figure 6.3) or a device without a captive cable (signal applied at test point TP3 of Figure 6.3). The corresponding signal levels and timings are given in the table below. Timings are given as a percentage of the unit interval (UI), which represents the nominal bit duration for a 480 Mbit/s transmi
