ページ1に含まれる内容の要旨
REJ09B0163-0100Z
H8S/2111B
16
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family / H8S/2100 Series
H8S/2111B HD64F2111B
Rev.1.00
Revision Date: May. 14, 2004
ページ2に含まれる内容の要旨
Rev. 1.00, 05/04, page ii of xxxiv
ページ3に含まれる内容の要旨
Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammabl
ページ4に含まれる内容の要旨
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins.
ページ5に含まれる内容の要旨
Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Des
ページ6に含まれる内容の要旨
Preface The H8S/2111B is a microcomputer (MCU) made up of the H8S/2000 CPU employing Renesas Technology's original architecture as its core, and the peripheral functions required to configure a system. The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a 16-Mbyte linear address space. This LSI is equipped with ROM, RAM, a 16-bit free-running timer (FRT),
ページ7に含まれる内容の要旨
Rules: Register name: The following notation is used for cases when the same or a similar function, e.g. serial communication interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) Bit order: The MSB is on the left and the LSB is on the right. Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. Signal notation: An overbar is added to a low-active signal: xxxx Related Manuals: The latest versions of all
ページ8に含まれる内容の要旨
Rev. 1.00, 05/04, page viii of xxxiv
ページ9に含まれる内容の要旨
Contents Section 1 Overview............................................................................................1 1.1 Features............................................................................................................................. 1 1.2 Internal Block Diagram..................................................................................................... 2 1.3 Pin Description....................................................................................
ページ10に含まれる内容の要旨
2.8 Processing States...............................................................................................................46 2.9 Usage Notes ...................................................................................................................... 48 2.9.1 Note on TAS Instruction Usage........................................................................... 48 2.9.2 Note on STM/LDM Instruction Usage ................................................................ 48 2
ページ11に含まれる内容の要旨
5.4.1 External Interrupts ............................................................................................... 76 5.4.2 Internal Interrupts ................................................................................................ 77 5.5 Interrupt Exception Handling Vector Table...................................................................... 78 5.6 Interrupt Control Modes and Interrupt Operation ............................................................. 80 5.6.1 Int
ページ12に含まれる内容の要旨
7.4 Port 4................................................................................................................................. 107 7.4.1 Port 4 Data Direction Register (P4DDR)............................................................. 107 7.4.2 Port 4 Data Register (P4DR) ............................................................................... 107 7.4.3 Pin Functions ....................................................................................................... 1
ページ13に含まれる内容の要旨
7.12.5 Pin Functions ....................................................................................................... 135 7.12.6 Input Pull-Up MOS in Ports C and D .................................................................. 135 7.13 Ports E, F........................................................................................................................... 136 7.13.1 Port E and Port F Data Direction Registers (PEDDR, PFDDR) .......................... 136 7.13.2 Port E a
ページ14に含まれる内容の要旨
9.3.7 Timer Control/Status Register (TCSR)................................................................ 163 9.3.8 Timer Control Register (TCR)............................................................................. 166 9.3.9 Timer Output Compare Control Register (TOCR) .............................................. 167 9.4 Operation .......................................................................................................................... 169 9.4.1 Pulse Output .......
ページ15に含まれる内容の要旨
10.5.1 TCNT Count Timing ........................................................................................... 207 10.5.2 Timing of CMFA and CMFB Setting at Compare-Match ................................... 207 10.5.3 Timing of Timer Output at Compare-Match........................................................ 208 10.5.4 Timing of Counter Clear at Compare-Match....................................................... 208 10.5.5 TCNT External Reset Timing................................
ページ16に含まれる内容の要旨
11.6.5 System Reset by RESO Signal ............................................................................ 233 11.6.6 Counter Values during Transitions between High-Speed, Sub-Active, and Watch Modes ................................................................................................ 233 Section 12 Serial Communication Interface (SCI)............................................235 12.1 Features...............................................................................
ページ17に含まれる内容の要旨
12.8.6 SCI Operations during Mode Transitions ............................................................ 273 12.8.7 Switching from SCK Pins to Port Pins ................................................................ 276 2 Section 13 I C Bus Interface (IIC) .....................................................................277 13.1 Features............................................................................................................................. 277 13.2 Input/Output
ページ18に含まれる内容の要旨
14.4.6 KBF Setting Timing and KCLK Control............................................................. 362 14.4.7 Receive Timing.................................................................................................... 363 14.4.8 KCLK Fall Interrupt Operation ........................................................................... 364 14.5 Usage Notes ...................................................................................................................... 365 14.5.
ページ19に含まれる内容の要旨
16.4.2 Scan Mode ........................................................................................................... 419 16.4.3 Input Sampling and A/D Conversion Time ......................................................... 421 16.4.4 External Trigger Input Timing............................................................................. 422 16.5 Interrupt Sources...............................................................................................................423 16.6
ページ20に含まれる内容の要旨
19.2 Duty Correction Circuit .................................................................................................... 459 19.3 Medium-Speed Clock Divider .......................................................................................... 459 19.4 Bus Master Clock Select Circuit....................................................................................... 459 19.5 Subclock Input Circuit ................................................................................
