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User’s Manual
m PD78058F, 78058FY Subseries
8-Bit Single-Chip Microcontrollers
m PD78056F
m PD78058F
m PD78P058F
m PD78058F(A)
m PD78056FY
m PD78058FY
m PD78P058FY
m PD78058FY(A)
Document No. U12068EJ2V0UM00 (2nd edition)
Date Published April 1998 N CP (K)
© 1997
Printed in Japan
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[MEMO] 2
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build stati
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The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. 2 2
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Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and compo
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MAJOR REVISIONS IN THIS EDITION Page Major Revision from Previous Edition Throughout The following products have already been developed: μPD78056FGC-×××-8BT, 78058FGC-×××-8BT, 78P058FGC-8BT, 78056FYGC-×××-8BT, 78058FYGC-×××-8BT P133 to The block diagrams of the following ports were changed. P137, P143 Figures 6-5 and 6-7 P20, P21, P23 to P26 Block Diagram, Figures 6-6 and 6-8 P22 and P27 Block Diagram, Figure 6-9 P30 to P37 Block Diagram, Figure 6-16 P71 and P72 Block Diagram P159 Table 7-2
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PREFACE Readers This manual has been prepared for user engineers who want to understand the functions of the μPD78058F and 78058FY Subseries and design and develop its application systems and programs. Affected versions are each of the versions in the following Subseries. μPD78058F Subseries : μPD78056F, 78058F, 78P058F, 78058F(A) μPD78058FY Subseries : μPD78056FY, 78058FY, 78P058FY, 78058FY(A) Purpose This manual is intended for users to understand the functions described in the Organization b
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How to Read This Manual Before reading this manual, you should have general knowledge of electric and logic circuits and microcontrollers. For persons who use this manual as the manual for the μPD78058F(A) and 78058FY(A), → The μPD78058F and 78058FY differ from the μPD78058F(A) and 78058FY(A) only in their quality grades. For products with (A), please change the readings for the product name as follows. μPD78058F → μPD78058F(A) μPD78058FY → μPD78058FY(A) When you want to understand the function
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Chapter Organization This manual divides the descriptions for the μPD78058F and 78058FY Subseries into different chapters as shown below. Read only the chapters related to the device you use. Chapter μPD78058F Subseries μPD78058FY Subseries Chapter 1 Outline (μPD78058F Subseries) √ — Chapter 2 Outline (μPD78058FY Subseries) — √ Chapter 3 Pin Function (μPD78058F Subseries) √ — Chapter 4 Pin Function (μPD78058FY Subseries) — √ Chapter 5 CPU Architecture √√ Chapter 6 Port Functions √√ Chapter 7 Cl
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Differences between μPD78058F and μPD78058FY Subseries: The μPD78058F and μPD78058FY Subseries are different in the following functions of the serial interface channel 0. Modes of Serial Interface Channel 0 μPD78058F μPD78058FY Subseries Subseries 3-wire serial I/O mode √√ 2-wire serial I/O mode √√ SBI (serial bus interface) mode √ — 2 I C bus mode — √ √ : Supported — : Not supported Conventions Data significance : Higher digits on the left and lower digits on the right Active low representation
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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Related Documents for μPD78058F Subseries Document No. Document Name Japanese English μPD78056F, 78058F Data Sheet U11795J U11795E μPD78P058F Data Sheet U11796J U11796E μPD78058F(A) Data Sheet U12325J U12325E μPD78058F, 78058FY Subseries User’s Manual U12068J This manual 78K/0 Series User’s Manual—Instruction U12326J U12326E 78K/0 Series I
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Development Tool Documents (User’s Manuals) Document No. Document Name Japanese English RA78K0 Assembler Package Operation U11802J U11802E Assembly language U11801J U11801E Structured assembler language U11789J U11789E RA78K Series Structured Assembler Preprocessor U12323J EEU-1402 CC78K0 C Compiler Operation U11517J U11517E Language U11518J U11518E CC78K0 C Compiler Application Note Programming know-how U13034J EEA-1208 CC78K Series Library Source File U12322J — PG-1500 PROM Programmer U
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Documents for Embedded Software (User’s Manual) Document No. Document Name Japanese English 78K/0 Series Real-Time OS Basics U11537J U11537E Installation U11536J U11536E OS for 78K/0 Series MX78K0 Basics U12257J U12257E Other Documents Document No. Document Name Japanese English IC PACKAGE MANUAL C10943X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grade on NEC Semiconductor Devices C11531J C11531E Reliability Quality Control on NEC Semiconductor Devices C10983J C10983
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[MEMO] 14
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CONTENTS CHAPTER 1 OUTLINE (μPD78058F SUBSERIES) ............................................................................. 35 1.1 Features .................................................................................................................................. 35 1.2 Applications ........................................................................................................................... 36 1.3 Ordering Information .....................................................
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3.2.14 AVSS.............................................................................................................................................. 71 3.2.15 RESET ......................................................................................................................................... 71 3.2.16 X1 and X2 .................................................................................................................................... 71 3.2.17 XT1 and XT2 .................
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5.2.1 Control registers ........................................................................................................................... 103 5.2.2 General registers .......................................................................................................................... 106 5.2.3 Special Function Register (SFR) .................................................................................................. 108 5.3 Instruction Address Addressing .....................
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7.4.2 Subsystem clock oscillator ........................................................................................................... 162 7.4.3 Scaler ........................................................................................................................................... 164 7.4.4 When no subsystem clocks are used ........................................................................................... 164 7.5 Clock Generator Operations ...............................
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CHAPTER 11 WATCHDOG TIMER ...................................................................................................... 245 11.1 Watchdog Timer Functions ................................................................................................ 245 11.2 Watchdog Timer Configuration .......................................................................................... 247 11.3 Watchdog Timer Control Registers ....................................................................
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16.4.3 SBI mode operation ................................................................................................................. 305 16.4.4 2-wire serial I/O mode operation ............................................................................................. 331 16.4.5 SCK0/P27 pin output manipulation ......................................................................................... 336 CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (m PD78058FY SUBSERIES)......................
