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MVME172
VME Embedded Controller
Programmer’s
Reference Guide
VME172A/PG2
Edition of February 1999
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Notice While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes. No part of this material may be reproduced or copied in any tangible medium, or
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Preface This manual provides board level information and detailed ASIC chip information including register bit descriptions for the MVME172 Embedded Controller. The information contained in this manual applies to the following MVME172 models: MVME172-303 MVME172-213 MVME172-313 MVME172-413 MVME172-513 MVME172-223 MVME172-323 MVME172-233 MVME172-333 MVME172-433 MVME172-243 MVME172-343 MVME172-253 MVME172-353 MVME172-453 MVME172-263 MVME172-363 MVME172-373 This manual is intended for anyo
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In this manual, assertion and negation are used to specify forcing a signal to a particular state. In particular, assertion and assert refer to a signal that is active or true; negation and negate indicate a signal that is inactive or false. These terms are used independently of the voltage level (high or low) that they represent. Data and address sizes are defined as follows: ❏ A byte is eight bits, numbered 0 through 7, with bit 0 being the least significant. ❏ A word is 16 bits, numbere
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The computer programs stored in the Read Only Memory of this device contain material copyrighted by Motorola Inc., first published 1990, and may be used only under a license such as the License for Computer Programs (Article 14) contained in Motorola’s Terms and Conditions of Sale, Rev. 1/79. This equipment generates, uses, and can radiate electro- magnetic energy. It may cause or be susceptible to electro-magnetic ! interference (EMI) if not installed and used in a cabinet with WARNING ad
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Place holder
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Contents CHAPTER 1 Board Description and Memory Maps Introduction................................................................................................................1-1 Overview....................................................................................................................1-1 Requirements .............................................................................................................1-4 Block Diagrams ..................................................
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DMAC TEA - Cause Unidentified............................................................ 1-54 LAN Parity Error....................................................................................... 1-54 LAN Off-Board Error ............................................................................... 1-55 LAN LTO Error ........................................................................................ 1-55 SCSI Parity Error .................................................................
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VMEbus Slave Address Translation Select Register 1 ............................2-30 VMEbus Slave Address Translation Address Offset Register 2 ...............2-31 VMEbus Slave Address Translation Select Register 2 ............................2-31 VMEbus Slave Write Post and Snoop Control Register 2 ........................2-32 VMEbus Slave Address Modifier Select Register 2 .................................2-33 VMEbus Slave Write Post and Snoop Control Register 1 ........................2-35 VME
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MPU Status and DMA Interrupt Count Register ..................................... 2-63 DMAC Status Register ............................................................................. 2-64 Programming the Tick and Watchdog Timers.................................................. 2-65 VMEbus Arbiter Time-out Control Register ........................................... 2-65 DMAC Ton/Toff Timers and VMEbus Global Time-out Control Register .............................. 2-66 VME Access, Local Bus,
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Interrupt Level Register 4 (bits 24-31) .....................................................2-94 Interrupt Level Register 4 (bits 16-23) .....................................................2-95 Interrupt Level Register 4 (bits 8-15) .......................................................2-95 Interrupt Level Register 4 (bits 0-7) .........................................................2-96 Vector Base Register ................................................................................2-96
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Local Bus Timer ................................................................................................. 3-8 Memory Map of the MC2 Chip Registers ................................................................. 3-8 Programming Model................................................................................................ 3-10 MC2 Chip ID Register ..................................................................................... 3-11 MC2 Chip Revision Register .................
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CHAPTER 4 IP2 Chip Introduction................................................................................................................4-1 Summary of Major Features ...............................................................................4-1 Functional Description...............................................................................................4-2 General Description ............................................................................................4-2 Cache C
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IP to Local Bus Data Routing.................................................................................. 4-52 Memory Space Accesses .................................................................................. 4-52 I/O and ID Space Accesses .............................................................................. 4-54 CHAPTER 5 MCECC Introduction ............................................................................................................... 5-1 Features...........
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Scrub Control Register......................................................................................5-23 Scrub Period Register Bits 15-8........................................................................5-24 Scrub Period Register Bits 7-0..........................................................................5-24 Chip Prescaler Counter .....................................................................................5-25 Scrub Time On/Time Off Register..........................
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FIGURES Figure 1-1. 200/300-Series MVME172 Block Diagram ........................................... 1-6 Figure 1-2. 400/500-Series MVME172 Block Diagram ........................................... 1-7 Figure 2-1. VMEchip2 Block Diagram ..................................................................... 2-5 TABLES Table 1-1. MVME172 Features Summary................................................................. 1-3 Table 1-2. Redundant Functions in the VMEchip2 and MC2 Chip .................
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Table 5-1. MCECC Specifications.............................................................................5-3 Table 5-2. MCECC Internal Register Memory Map, Part 1 ....................................5-10 Table 5-3. MCECC Internal Register Memory Map, Part 2 ...................................5-12 Table A-1. Motorola Computer Group Documents ..................................................A-1 Table A-2. Manufacturers’ Documents ................................................................
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1Board Description 1 and Memory Maps Introduction This manual provides programming information for the MVME172 Embedded Controller. Extensive programming information is provided for the Application-Specific Integrated Circuit (ASIC) devices used on the board. Reference information is included for the Large Scale Integration (LSI) devices used on the board and sources for additional information are provided. This chapter briefly describes the board level hardware features of the MVME172 Em
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Board Description and Memory Maps 1 The I/O connection for the 400/500-Series serial ports is provided by two DB-25 front panel I/O connectors. The I/O is connected to the VMEbus P2 connector. The main board is connected through a P2 transition board and cables to transition boards. The Series 400/500 MVME172 supports the transition boards MVME712-12, MVME712-13, MVME712M, MVME712A, MVME712AM, and MVME712B (referred to in this manual as MVME712x, unless separately specified). These transit
