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DYNAMIC ENGINEERING
435 Park Dr., Ben Lomond, Calif. 95005
831-336-8891 Fax 831-336-3840
sales@dyneng.com
www.dyneng.com
Est. 1988
User Manual
PMC-4U-CACI
Quad UART - Dual Synchronous
Serial Data Interface
PMC Module
Revision OR
Corresponding Hardware: Revision 01
ページ2に含まれる内容の要旨
This document contains information of proprietary PMC-4U interest to Dynamic Engineering. It has been supplied Quad UART - Dual Synchronous in confidence and the recipient, by accepting this Serial Data Interface material, agrees that the subject matter will not be copied or reproduced, in whole or in part, nor its PMC Module contents revealed in any manner or to any person except to meet the purpose for which it was delivered. Dynamic Engineering Dynamic Engineering has made every effort to ens
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Table of Contents PRODUCT DESCRIPTION 6 THEORY OF OPERATION 9 ADDRESS MAP 10 PROGRAMMING 12 REGISTER DEFINITIONS 13 PMC4U_BASE 13 PMC4U_STAT 16 PMC4U_MSK 16 PMC4U_SCC_IVEC 17 PMC4U_DIR_TERM 17 PMC4U_SW_IN 18 PMC4U_SCC_A_CNTL 19 PMC4U_SCC_A_DATA 19 PMC4U_SCC_B_CNTL 19 PMC4U_SCC_B_DATA 19 PMC4U_UART_A 20 PMC4U_UART_B 20 PMC4U_UART_C 20 PMC4U_UART_D 20 PMC4U_IRUPT/PMC4U_IRUPT_CLR 21 Interrupts 22 Loop-back 23 PMC PCI PN1 INTERFACE PIN ASSIGNMENT 24 PMC PCI PN2 INTERFACE PIN ASSIGNMENT 25 PMC-4U FRO
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Interfacing 28 CONSTRUCTION AND RELIABILITY 29 THERMAL CONSIDERATIONS 29 WARRANTY AND REPAIR 30 SERVICE POLICY 31 OUT OF WARRANTY REPAIRS 31 FOR SERVICE CONTACT: 31 SPECIFICATIONS 32 ORDER INFORMATION 33 SCHEMATICS 33 Hardware and Software Design • Manufacturing Services P a g e 4
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List of Figures FIGURE 1 PMC-4U BLOCK DIAGRAM 6 FIGURE 2 PMC-4U INTERNAL ADDRESS MAP 10 FIGURE 3 PMC-4U UART ADDRESS MAP 11 FIGURE 4 PMC-4U BASE CONTROL REGISTER BIT MAP 13 FIGURE 5 PMC-4U TX CONTROL REGISTER BIT MAP 16 FIGURE 6 PMC-4U INTERRUPT MASK REGISTER BIT MAP 16 FIGURE 7 PMC-4U DIRECTION TERMINATION CONTROL BIT MAP 17 FIGURE 8 PMC-4U SWITCH READ BIT MAP 18 FIGURE 9 PMC-4U INTERRUPT STATUS/CLEAR 21 FIGURE 10 PMC-4U PN1 INTERFACE 24 FIGURE 11 PMC-4U PN2 INTERFACE 25 FIGURE 12 PMC-4U FRONT
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Product Description PMC-4U-CACI is part of the PMC Module family of modular I/O components by Dynamic Engineering. The PMC-4U is capable of providing multiple serial protocols both synchronous and asynchronous with a wide range of baud rates. The CACI interface uses an RS-423 driver, an RS-422 driver, and an RS-422 receiver for each UART channel. Two enhanced hysteresis MIL STD 188-114A receivers, a MIL STD 188-114A driver, and an open drain active low output driver for one synchronous channel
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An EXAR XR16C854 implements the UART interface. This quad UART device is compatible with the industry standard 16550 UART, but is equipped with 128 byte FIFOs, independent Tx and Rx FIFO counters, automatic hardware/software flow control, and many other enhanced features. An 18.432 MHz oscillator supplies the reference clock for this device allowing baud rates up to 1.152 Mbps. The synchronous interface uses a Zilog Serial Communication Controller, the Z85C30. This dual channel, multi-protoco
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There is also a master interrupt enable that can be set to gate the interrupt onto the PCI bus. The interrupt status is still available in a status register even when the master interrupt enable is off. This facilitates polled operation of interrupt conditions. The individual interrupt conditions are specified in the internal registers of the UART and SCC. Please see the XR16C854 and Z85C30 documentation for more information on interrupt conditions and configuration. Hardware and Softwar
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Theory of Operation The PMC-4U is designed for transferring data from one point to another with a variety of serial protocols. The PMC-4U features a Xilinx FPGA. The FPGA contains the general control and status registers as well as the interface to the quad UART, SCC, and IO drivers and receivers. Many additional control and status registers reside in the UART and SCC, which are accessed through the Xilinx interface. The PMC-4U is a part of the PMC Module family of modular I/O products. It meets
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Address Map REGISTER OFFSET FUNCTION TYPE PMC4U_BASE 0X00 base control read/write PMC4U_STAT 0X04 status read read PMC4U_MSK 0X08 interrupt mask control read/write PMC4U_SCC_IVEC 0X0C SCC interrupt vector read read PMC4U_DIR_TERM 0X10 direction and termination control read/write PMC4U_SW_IN 0X14 read user switch read PMC4U_SCC_A_CNTL 0X18 SCC channel A control read/write PMC4U_SCC_A_DATA 0X1C SCC channel A data read/write PMC4U_SCC_B_CNTL 0X20 SCC channel B control read/write PMC4U_SCC_B_DATA 0
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REGISTER OFFSET FUNCTION PMC4U_UART_DATA 0X00 UART read/write data PMC4U_UART_IEN 0X04 UART write interrupt enable PMC4U_UART_ISTAT 0X08 UART read interrupt status PMC4U_UART_FCNTL 0X08 UART write FIFO control PMC4U_UART_LCNTL 0X0C UART write line control PMC4U_UART_MCNTL 0X10 UART write modem control PMC4U_UART_LSTAT 0X14 UART read line status PMC4U_UART_MSTAT 0X18 UART read modem status PMC4U_UART_SPAD 0X1C UART read/write scratchpad UART baud rate register defines (enabled when *LCNTL bit-
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Programming Programming the PMC-4U requires only the ability to read and write data from the host. The base address is determined by the PMC Carrier board. The base address refers to the first user address for the slot in which the PMC is installed. Depending on the software environment it may be necessary to set-up the system software with the PMC-4U "registration" data. For example in WindowsNT there is a system registry, which is used to identify the resident hardware. The PMC-4U VendorId =
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Register Definitions PMC4U_BASE [0X00] PMC-4U Control Register Port read/write CONTROL BASE DATA BIT DESCRIPTION 31-22 spare 21-20 test mode select 19 master interrupt enable 18 force interrupt 17 SCC reset 16 UART reset 15-0 spare FIGURE 4 PMC-4U BASE CONTROL REGISTER BIT MAP All bits are active high and are reset on power-up or reset command. Test mode select is used to enable different drivers and receivers to allow thorough testing of the IO circuitry. A value of “00” indicates normal op
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SCC Tx A OUT_4 (188) SCC Rx A AUX_IN_0 (enhanced hysteresis 188) SCC Rx Clk AUX_IN_1 (enhanced hysteresis 188) SCC RTS A AUX_OUT_0 (open drain) SCC Tx B IO_15 (RS422) SCC Rx B IO_13 (RS422) When test mode select is “10” the following changes are made (if a signal is not listed here, its connection remains the same): Signal Function Driver/Receiver UART Rx A IO_1 (RS422) UART Rx B IO_3 (RS422) UART Rx C IO_5 (RS422) UART Rx D IO_7 (RS422) SCC RTS A AUX_OUT_1 (open drain) SCC Tx B IO_14 (RS422
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UART Tx C OUT_6 (RS423) UART Rx C IN_6 (RS232) UART Tx D OUT_7 (RS423) UART Rx D IN_7 (RS232) Master interrupt enable when ‘1’ gates all interrupts through to the PCI host. When ‘0’ the interrupts can be used for status without interrupting the host. Force interrupt is used for test and software development purposes to create an interrupt request. 1 = assert interrupt request. 0 = normal operation. Useful to stimulate interrupt acknowledge routines for development. SCC reset causes a hard
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PMC4U_STAT [0X04] PMC-4U Status Port read only STATUS DATA BIT DESCRIPTION 31-2 spare 1 interrupt out 0 interrupt status FIGURE 5 PMC-4U TX CONTROL REGISTER BIT MAP Interrupt out indicates that an interrupt is asserted on the PCI bus. Interrupt status indicates that an interrupt condition exists, however if the master interrupt enable is not asserted, then the interrupt will not be asserted on the PCI bus. This bit can be used to operate the card in polled mode without interrupting the host
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PMC4U_SCC_IVEC [0X0C] PMC-4U SCC Interrupt Acknowledge/Vector Read A read from this address causes the SCC interrupt acknowledge signal to be asserted. If an interrupt condition exists in the SCC, it will respond by placing an interrupt vector on the local data bus. This vector is specified by the user and, depending on the state set in the SCC registers, may contain status information about the cause of the interrupt. PMC4U_DIR_TERM [0X10] PMC-4U Direction and Termination Port read/write CONT
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Parallel termination resistors are supplied on each differential pair along with a switch to allow the user to select which lines are terminated and where. In some systems it will make sense to terminate the lines in the cable and in others it will make sense to use the onboard terminations. CONTROL CORRESPONDING IO BITS TERM0 IO_0..7 TERM1 IO_8..11 TERM2 IO_12..13 TERM3 IO_14..15 PMC4U_SW_IN [0X14] PMC-4U User Switch Port read only USER CONTROL SWITCH REGISTER DATA BIT DESCRIPTION 5 U
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PMC4U_SCC_A_CNTL [0X18] PMC-4U SCC Channel A Control Register read/write This address is used to access all of the channel A registers. In order to access a register other than this base register, the register number is first written to this address. A subsequent read or write will read from or write to the desired register. After this process is completed, the pointers are reset so that the base register is once again accessed. See the Z85C30 documentation for more information on this proce
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PMC4U_UART_A [0X40] PMC-4U UART A Base Address This is the base address for the eight register addresses associated with UART A. Figure 3 gives an overview of these registers and their functions. For more details on the access and functions of these registers see the XR16C854 documentation. PMC4U_UART_B [0X60] PMC-4U UART B Base Address This is the base address for the eight register addresses associated with UART B. Figure 3 gives an overview of these registers and their functions. For more d
